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| author | Stephen George <stephen.george@freescale.com> | 2013-03-25 07:40:12 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-05-24 16:54:12 -0500 |
| commit | 49e946cb6ae0448492147ffcb9dcd7d0af1eab4d (patch) | |
| tree | 07118135410c7b399c8ac780b6fa803ceebdfaea /board/syteco | |
| parent | 94025b1cd8d9959ebf987a7f6382d513c606ecf1 (diff) | |
| download | u-boot-imx-49e946cb6ae0448492147ffcb9dcd7d0af1eab4d.zip u-boot-imx-49e946cb6ae0448492147ffcb9dcd7d0af1eab4d.tar.gz u-boot-imx-49e946cb6ae0448492147ffcb9dcd7d0af1eab4d.tar.bz2 | |
board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M
Debug trace buffers are memory mapped in DCSR space beyond 4M.
Signed-off-by: Stephen George <stephen.george@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/syteco')
0 files changed, 0 insertions, 0 deletions