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authorAlexey Brodkin <abrodkin@synopsys.com>2015-04-13 13:37:05 +0300
committerAlexey Brodkin <abrodkin@synopsys.com>2015-07-01 17:17:27 +0300
commit8b2eb776b13055e71f94367c06a26c5e3a902f16 (patch)
treeaad534710ed24ea662d54446c0e928b1b52c1ce1 /board/synopsys
parent9c6b05cb724e18d1db3f9e1a75b2272572f06fbd (diff)
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arc: implement slave cores kick-start for Linux kernel
With new SMP-enabled CPUs with ARC HS38 cores and corresponding support in Linux kernel it's required to add basic SMP support in U-Boot. Currently we assume the one and only core starts execution after power-on. So most of things in U-Boot is handled in UP mode. But when U-Boot is used for loading and starting Linux kernel right before jumping to kernel's entry point U-Boot: [1] Sets all slave cores to jump to the same address [kernel's entry point] [2] Really starts all slav cores In ARC's implemetation of SMP in Linux kernel all cores are supposed to run the same start-up code. But only core with ID 0 (master core) processes further while others are looping waiting for master core to complete some initialization. That means it's safe to un-pause slave cores and let them execute kernel - they will wait for master anyway. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'board/synopsys')
-rw-r--r--board/synopsys/axs101/axs101.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c
index 8c16410..d4280f7 100644
--- a/board/synopsys/axs101/axs101.c
+++ b/board/synopsys/axs101/axs101.c
@@ -56,3 +56,33 @@ int board_early_init_f(void)
return 0;
}
+
+#ifdef CONFIG_ISA_ARCV2
+#define RESET_VECTOR_ADDR 0x0
+
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+ /* All cores have reset vector pointing to 0 */
+ writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
+
+ /* Make sure other cores see written value in memory */
+ flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int));
+}
+
+void smp_kick_all_cpus(void)
+{
+/* CPU start CREG */
+#define AXC003_CREG_CPU_START 0xF0001400
+
+/* Bits positions in CPU start CREG */
+#define BITS_START 0
+#define BITS_POLARITY 8
+#define BITS_CORE_SEL 9
+#define BITS_MULTICORE 12
+
+#define CMD (1 << BITS_MULTICORE) | (1 << BITS_CORE_SEL) | \
+ (1 << BITS_POLARITY) | (1 << BITS_START)
+
+ writel(CMD, (void __iomem *)AXC003_CREG_CPU_START);
+}
+#endif