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authorChen-Yu Tsai <wens@csie.org>2014-06-09 11:37:01 +0200
committerIan Campbell <ijc@hellion.org.uk>2014-07-06 20:12:45 +0100
commitef7e723ba184a5664e6e27f1b92cd8fc2042d695 (patch)
treed026142b70bea10be6739b1292fa19d970d2d6c4 /board/sunxi
parentc26fb9db0ed7d524bde1206ed49a63e50125d329 (diff)
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sunxi: Add support for using MII phy-s with the GMAC nic
Many A20 boards (ie Cubieboard2, A20-OLinuXino_MICRO) use an 100 Mbit MII phy together with the GMAC nic found in the A20 SoC, add support for this (this will get used when we add these boards in a later patch). Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'board/sunxi')
-rw-r--r--board/sunxi/gmac.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index e48328d..e7ff952 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -16,17 +16,28 @@ int sunxi_gmac_initialize(bd_t *bis)
setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
/* Set MII clock */
+#ifdef CONFIG_RGMII
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
CCM_GMAC_CTRL_GPIT_RGMII);
+#else
+ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
+ CCM_GMAC_CTRL_GPIT_MII);
+#endif
/* Configure pin mux settings for GMAC */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
+#ifdef CONFIG_RGMII
/* skip unused pins in RGMII mode */
if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
continue;
+#endif
sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
+#ifdef CONFIG_RGMII
return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
+#else
+ return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
+#endif
}