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authorHans de Goede <hdegoede@redhat.com>2014-10-03 16:44:57 +0200
committerHans de Goede <hdegoede@redhat.com>2014-10-24 09:35:38 +0200
commitbbff84b3b0092d00db1b0b77ef9043b46991d791 (patch)
tree44c991c8d262e36d05321be0d8f0da6de6716d4f /board/sunxi
parente79c7c881047ca99191cc79b6d83ec64b898cd9b (diff)
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sunxi: Use PG3 - PG8 as io-pins for mmc1
None of the known sunxi devices actually use mmc1 routed through PH, where as some devices do actually use mmc1 routed through PG, so change the routing of mmc1 to PG. If in the future we encounter devices with mmc1 routed through PH, we will need to change things to be a bit more flexible. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'board/sunxi')
-rw-r--r--board/sunxi/board.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index f310e8d..03890c8 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -71,9 +71,9 @@ static void mmc_pinmux_setup(int sdc)
break;
case 1:
- /* CMD-PH22, CLK-PH23, D0~D3-PH24~27 : 5 */
- for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1);
+ /* CMD-PG3, CLK-PG4, D0~D3-PG5-8 */
+ for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN5I_GPG3_SDC1);
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}