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authorSiarhei Siamashka <siarhei.siamashka@gmail.com>2015-02-01 00:27:06 +0200
committerHans de Goede <hdegoede@redhat.com>2015-02-02 14:04:23 +0100
commit47e3501a76894f4ba08bc61f33774bd5d39ff464 (patch)
treed2c69795669344a7324981526ba62b8b73d7511a /board/sunxi/Kconfig
parentd133647af4d4fdaaf2dfb6a9e757c7aebd00a29e (diff)
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sunxi: dram: Support more sun[457]i dram parameters in Kconfig
This patch allows to configure all the important DRAM parameters in Kconfig. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'board/sunxi/Kconfig')
-rw-r--r--board/sunxi/Kconfig43
1 files changed, 43 insertions, 0 deletions
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index da4e8ba..4a21589 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -41,6 +41,15 @@ config DRAM_CLK
Set the dram clock speed, valid range 240 - 480, must be a multiple
of 24.
+if MACH_SUN5I || MACH_SUN7I
+config DRAM_MBUS_CLK
+ int "sunxi mbus clock speed"
+ default 300
+ ---help---
+ Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
+
+endif
+
config DRAM_ZQ
int "sunxi dram zq value"
default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
@@ -56,6 +65,40 @@ config DRAM_EMR1
---help---
Set the dram controller emr1 value.
+config DRAM_ODT_EN
+ int "sunxi dram odt_en value"
+ default 0
+ ---help---
+ Set the dram controller odt_en parameter. This can be used to
+ enable/disable the ODT feature.
+
+config DRAM_TPR3
+ hex "sunxi dram tpr3 value"
+ default 0
+ ---help---
+ Set the dram controller tpr3 parameter. This parameter configures
+ the delay on the command lane and also phase shifts, which are
+ applied for sampling incoming read data. The default value 0
+ means that no phase/delay adjustments are necessary. Properly
+ configuring this parameter increases reliability at high DRAM
+ clock speeds.
+
+config DRAM_DQS_GATING_DELAY
+ hex "sunxi dram dqs_gating_delay value"
+ default 0
+ ---help---
+ Set the dram controller dqs_gating_delay parmeter. Each byte
+ encodes the DQS gating delay for each byte lane. The delay
+ granularity is 1/4 cycle. For example, the value 0x05060606
+ means that the delay is 5 quarter-cycles for one lane (1.25
+ cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
+ The default value 0 means autodetection. The results of hardware
+ autodetection are not very reliable and depend on the chip
+ temperature (sometimes producing different results on cold start
+ and warm reboot). But the accuracy of hardware autodetection
+ is usually good enough, unless running at really high DRAM
+ clocks speeds (up to 600MHz). If unsure, keep as 0.
+
choice
prompt "sunxi dram timings"
default DRAM_TIMINGS_VENDOR_MAGIC