stx: create common vendor/board hierarchy for STx boards

Move files belonging to the STx boards into common vendor directory and
update the Makefile to reflect this.

Signed-off-by: Alex Dubov <oakad@yahoo.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

7 files changed, 0 insertions, 888 deletions

diff --git a/board/stxssa/Makefile b/board/stxssa/Makefile
deleted file mode 100644
index 9ab41ec..0000000
--- a/board/stxssa/Makefile
+++ /dev/null
@@ -1,53 +0,0 @@
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).a
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-COBJS-$(CONFIG_FSL_DDR1) += ddr.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
-	rm -f $(OBJS) $(SOBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/stxssa/config.mk b/board/stxssa/config.mk
deleted file mode 100644
index 57fe5d6..0000000
--- a/board/stxssa/config.mk
+++ /dev/null
@@ -1,30 +0,0 @@
-# Modified by Xianghua Xiao, X.Xiao@motorola.com
-# (C) Copyright 2002,2003 Motorola Inc.
-#
-# Copied from ADS85xx for STx GP3 - Dan Malek
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-# default CCARBAR is at 0xff700000
-# assume U-Boot is less than 0.5MB
-# U-Boot is less than 256K, so push
-# it further up into the flash
-#
-TEXT_BASE = 0xFFFC0000
diff --git a/board/stxssa/ddr.c b/board/stxssa/ddr.c
deleted file mode 100644
index 93d1100..0000000
--- a/board/stxssa/ddr.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <i2c.h>
-
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
-
-static void
-get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
-{
-	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
-}
-
-
-unsigned int
-fsl_ddr_get_mem_data_rate(void)
-{
-	return get_ddr_freq(0);
-}
-
-
-void
-fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
-		      unsigned int ctrl_num)
-{
-	unsigned int i;
-	unsigned int i2c_address = 0;
-
-	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
-		if (ctrl_num == 0 && i == 0) {
-			i2c_address = SPD_EEPROM_ADDRESS;
-		}
-		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
-	}
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 0;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/* 2T timing enable */
-	popts->twoT_en = 1;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/stxssa/law.c b/board/stxssa/law.c
deleted file mode 100644
index 55dde66..0000000
--- a/board/stxssa/law.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
- * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
- * 0xe000_0000     0xe000_ffff     CCSR                    1M
- * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
- * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
- * 0xf000_0000     0xfaff_ffff     Local bus               128M
- * 0xfb00_0000     0xfb00_ffff     Config Latch            64K
- * 0xfc00_0000     0xffff_ffff     FLASH (boot bank)       64M
- *
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-#ifndef CONFIG_SPD_EEPROM
-	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
-#endif
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
-	/* Map the whole localbus, including flash and reset latch. */
-	SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c
deleted file mode 100644
index 73dddf3..0000000
--- a/board/stxssa/stxssa.c
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * (C) Copyright 2005, Embedded Alley Solutions, Inc.
- * Dan Malek, <dan@embeddedalley.com>
- * Copied from STx GP3.
- * Updates for Silicon Tx GP3 SSA
- *
- * (C) Copyright 2003,Motorola Inc.
- * Xianghua Xiao, (X.Xiao@motorola.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <ioports.h>
-#include <asm/io.h>
-#include <spd_sdram.h>
-#include <miiphy.h>
-#include <netdev.h>
-
-long int fixed_sdram (void);
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A configuration */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PA31 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TxENB */
-	/* PA30 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 TxClav	*/
-	/* PA29 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TxSOC  */
-	/* PA28 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 RxENB */
-	/* PA27 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RxSOC */
-	/* PA26 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RxClav */
-	/* PA25 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[0] */
-	/* PA24 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[1] */
-	/* PA23 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[2] */
-	/* PA22 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[3] */
-	/* PA21 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[4] */
-	/* PA20 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[5] */
-	/* PA19 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[6] */
-	/* PA18 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[7] */
-	/* PA17 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[7] */
-	/* PA16 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[6] */
-	/* PA15 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[5] */
-	/* PA14 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[4] */
-	/* PA13 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[3] */
-	/* PA12 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[2] */
-	/* PA11 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[1] */
-	/* PA10 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXD[0] */
-	/* PA9	*/ {   0,   1,	 1,   1,   0,	0   }, /* FCC1 L1TXD */
-	/* PA8	*/ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 L1RXD */
-	/* PA7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA7 */
-	/* PA6	*/ {   0,   1,	 1,   1,   0,	0   }, /* TDM A1 L1RSYNC */
-	/* PA5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA5 */
-	/* PA4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA4 */
-	/* PA3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA3 */
-	/* PA2	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA2 */
-	/* PA1	*/ {   1,   0,	 0,   0,   0,	0   }, /* FREERUN */
-	/* PA0	*/ {   0,   0,	 0,   1,   0,	0   }  /* PA0 */
-    },
-
-    /* Port B configuration */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PB31 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TX_ER */
-	/* PB30 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_DV */
-	/* PB29 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC2 MII TX_EN */
-	/* PB28 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_ER */
-	/* PB27 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII COL */
-	/* PB26 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII CRS */
-	/* PB25 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[3] */
-	/* PB24 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[2] */
-	/* PB23 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[1] */
-	/* PB22 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[0] */
-	/* PB21 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[0] */
-	/* PB20 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[1] */
-	/* PB19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[2] */
-	/* PB18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[3] */
-	/* PB17 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:RX_DIV */
-	/* PB16 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:RX_ERR */
-	/* PB15 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC3:TX_ERR */
-	/* PB14 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC3:TX_EN */
-	/* PB13 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:COL */
-	/* PB12 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:CRS */
-	/* PB11 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:RXD */
-	/* PB10 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:RXD */
-	/* PB9	*/ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:RXD */
-	/* PB8	*/ {   0,   1,	 0,   0,   0,	0   }, /* FCC3:RXD */
-	/* PB7	*/ {   0,   1,	 0,   1,   0,	0   }, /* FCC3:TXD */
-	/* PB6	*/ {   0,   1,	 0,   1,   0,	0   }, /* FCC3:TXD */
-	/* PB5	*/ {   0,   1,	 0,   1,   0,	0   }, /* FCC3:TXD */
-	/* PB4	*/ {   0,   1,	 0,   1,   0,	0   }, /* FCC3:TXD */
-	/* PB3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
-	/* PB2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
-	/* PB1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
-	/* PB0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
-    },
-
-    /* Port C */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PC31 */ {   0,   0,	 0,   1,   0,	0   }, /* PC31 */
-	/* PC30 */ {   0,   0,	 0,   1,   0,	0   }, /* PC30 */
-	/* PC29 */ {   0,   1,	 1,   0,   0,	0   }, /* SCC1 EN *CLSN */
-	/* PC28 */ {   0,   0,	 0,   1,   0,	0   }, /* PC28 */
-	/* PC27 */ {   0,   0,	 0,   1,   0,	0   }, /* UART Clock in */
-	/* PC26 */ {   0,   0,	 0,   1,   0,	0   }, /* PC26 */
-	/* PC25 */ {   0,   0,	 0,   1,   0,	0   }, /* PC25 */
-	/* PC24 */ {   0,   0,	 0,   1,   0,	0   }, /* PC24 */
-	/* PC23 */ {   0,   1,	 0,   1,   0,	0   }, /* ATMTFCLK */
-	/* PC22 */ {   0,   1,	 0,   0,   0,	0   }, /* ATMRFCLK */
-	/* PC21 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RXCLK */
-	/* PC20 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN TXCLK */
-	/* PC19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_CLK CLK13 */
-	/* PC18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC Tx Clock (CLK14) */
-	/* PC17 */ {   0,   0,	 0,   1,   0,	0   }, /* PC17 */
-	/* PC16 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC Tx Clock (CLK16) */
-	/* PC15 */ {   0,   1,	 0,   0,   0,	0   }, /* PC15 */
-	/* PC14 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CD */
-	/* PC13 */ {   0,   0,	 0,   1,   0,	0   }, /* PC13 */
-	/* PC12 */ {   0,   1,	 0,   1,   0,	0   }, /* PC12 */
-	/* PC11 */ {   0,   0,	 0,   1,   0,	0   }, /* LXT971 transmit control */
-	/* PC10 */ {   0,   0,	 0,   1,   0,	0   }, /* FETHMDC */
-	/* PC9	*/ {   0,   0,	 0,   0,   0,	0   }, /* FETHMDIO */
-	/* PC8	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC8 */
-	/* PC7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC7 */
-	/* PC6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC6 */
-	/* PC5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC5 */
-	/* PC4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC4 */
-	/* PC3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC3 */
-	/* PC2	*/ {   0,   0,	 0,   1,   0,	1   }, /* ENET FDE */
-	/* PC1	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET DSQE */
-	/* PC0	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET LBK */
-    },
-
-    /* Port D */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PD31 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RxD */
-	/* PD30 */ {   0,   1,	 1,   1,   0,	0   }, /* SCC1 EN TxD */
-	/* PD29 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC1 EN TENA */
-	/* PD28 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC2 RxD */
-	/* PD27 */ {   1,   1,	 0,   1,   0,	0   }, /* SCC2 TxD */
-	/* PD26 */ {   0,   0,	 0,   1,   0,	0   }, /* PD26 */
-	/* PD25 */ {   0,   0,	 0,   1,   0,	0   }, /* PD25 */
-	/* PD24 */ {   0,   0,	 0,   1,   0,	0   }, /* PD24 */
-	/* PD23 */ {   0,   0,	 0,   1,   0,	0   }, /* PD23 */
-	/* PD22 */ {   0,   0,	 0,   1,   0,	0   }, /* PD22 */
-	/* PD21 */ {   0,   0,	 0,   1,   0,	0   }, /* PD21 */
-	/* PD20 */ {   0,   0,	 0,   1,   0,	0   }, /* PD20 */
-	/* PD19 */ {   0,   0,	 0,   1,   0,	0   }, /* PD19 */
-	/* PD18 */ {   0,   0,	 0,   1,   0,	0   }, /* PD18 */
-	/* PD17 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXPRTY */
-	/* PD16 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXPRTY */
-	/* PD15 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SDA */
-	/* PD14 */ {   1,   1,	 1,   0,   0,	0   }, /* I2C CLK */
-	/* PD13 */ {   0,   0,	 0,   0,   0,	0   }, /* PD13 */
-	/* PD12 */ {   0,   0,	 0,   0,   0,	0   }, /* PD12 */
-	/* PD11 */ {   0,   0,	 0,   0,   0,	0   }, /* PD11 */
-	/* PD10 */ {   0,   0,	 0,   0,   0,	0   }, /* PD10 */
-	/* PD9	*/ {   0,   1,	 0,   1,   0,	0   }, /* SMC1 TXD */
-	/* PD8	*/ {   0,   1,	 0,   0,   0,	0   }, /* SMC1 RXD */
-	/* PD7	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD7 */
-	/* PD6	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD6 */
-	/* PD5	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD5 */
-	/* PD4	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD4 */
-	/* PD3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
-	/* PD2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
-	/* PD1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
-	/* PD0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
-    }
-};
-
-static	uint64_t	next_led_update;
-static	uint		led_bit;
-
-void
-reset_phy(void)
-{
-	volatile uint *blatch;
-#if 0
-	int	i;
-#endif
-	blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
-
-	/* reset Giga bit Ethernet port if needed here */
-
-#if 1
-	*blatch &= ~0x000000c0;
-	udelay(100);
-#else
-	*blatch = 0;
-	asm("eieio");
-	for (i=0; i<1000; i++)
-		udelay(1000);
-#endif
-	*blatch = 0x000000c1;	/* Light one led, too */
-	udelay(1000);
-
-#if 0	/* This is the port we really want to use for debugging. */
-	/* reset the CPM FEC port */
-#if (CONFIG_ETHER_INDEX == 2)
-	bcsr->bcsr2 &= ~FETH2_RST;
-	udelay(2);
-	bcsr->bcsr2 |=	FETH2_RST;
-	udelay(1000);
-#elif (CONFIG_ETHER_INDEX == 3)
-	bcsr->bcsr3 &= ~FETH3_RST;
-	udelay(2);
-	bcsr->bcsr3 |=	FETH3_RST;
-	udelay(1000);
-#endif
-#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
-	/* reset PHY */
-	miiphy_reset("FCC1 ETHERNET", 0x0);
-
-	/* change PHY address to 0x02 */
-	bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
-
-	bb_miiphy_write(NULL, 0x02, PHY_BMCR,
-			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
-#endif /* CONFIG_MII */
-#endif
-}
-
-int
-board_early_init_f(void)
-{
-#if defined(CONFIG_PCI)
-	volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
-
-	pci->peer &= 0xffffffdf; /* disable master abort */
-#endif
-
-	/* Why is the phy reset done _after_ the ethernet
-	 * initialization in lib_ppc/board.c?
-	 * Do it here so it's done before the TSECs are used.
-	 */
-	reset_phy();
-
-	return 0;
-}
-
-int
-checkboard(void)
-{
-	printf ("Board: Silicon Tx GPPP SSA Board\n");
-	return (0);
-}
-
-/* Blinkin' LEDS for Robert.
-*/
-void
-show_activity(int flag)
-{
-	volatile uint *blatch;
-
-	if (next_led_update > get_ticks())
-		return;
-
-	blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
-
-	led_bit >>= 1;
-	if (led_bit == 0)
-		led_bit = 0x08;
-	*blatch = (0xc0 | led_bit);
-	eieio();
-	next_led_update += (get_tbclk() / 4);
-}
-
-phys_size_t
-initdram (int board_type)
-{
-	long dram_size = 0;
-
-#if defined(CONFIG_DDR_DLL)
-	{
-		volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-		uint temp_ddrdll = 0;
-
-		/* Work around to stabilize DDR DLL */
-		temp_ddrdll = gur->ddrdllcr;
-		gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
-		asm("sync;isync;msync");
-	}
-#endif
-
-	dram_size = fsl_ddr_sdram();
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
-#if defined(CONFIG_DDR_ECC)
-	/* Initialize and enable DDR ECC.
-	*/
-	ddr_enable_ecc(dram_size);
-#endif
-
-	return dram_size;
-}
-
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int testdram (void)
-{
-	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
-	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
-	uint *p;
-
-	printf("SDRAM test phase 1:\n");
-	for (p = pstart; p < pend; p++)
-		*p = 0xaaaaaaaa;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	printf("SDRAM test phase 2:\n");
-	for (p = pstart; p < pend; p++)
-		*p = 0x55555555;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	printf("SDRAM test passed.\n");
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_PCI)
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_stxgp3_config_table[] = {
-    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-      PCI_IDSEL_NUMBER, PCI_ANY_ID,
-      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
-				   PCI_ENET0_MEMADDR,
-				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
-      } },
-    { }
-};
-#endif
-
-
-static struct pci_controller hose[] = {
-#ifndef CONFIG_PCI_PNP
-	{ config_table: pci_stxgp3_config_table,},
-#else
-	{},
-#endif
-#ifdef CONFIG_MPC85XX_PCI2
-	{},
-#endif
-};
-
-#endif	/* CONFIG_PCI */
-
-
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
-	extern void pci_mpc85xx_init(struct pci_controller *hose);
-
-	pci_mpc85xx_init(hose);
-#endif /* CONFIG_PCI */
-}
-
-int board_eth_init(bd_t *bis)
-{
-	cpu_eth_init(bis);	/* Initialize TSECs first */
-	return pci_eth_init(bis);
-}
diff --git a/board/stxssa/tlb.c b/board/stxssa/tlb.c
deleted file mode 100644
index 0386432..0000000
--- a/board/stxssa/tlb.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/*
-	 * TLB 0:	64M	Non-cacheable, guarded
-	 * 0xfc000000	6M4	FLASH
-	 * Out of reset this entry is only 4K.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLB 1:	256M	Non-cacheable, guarded
-	 * 0x80000000	256M	PCI1 MEM First half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 2:	256M	Non-cacheable, guarded
-	 * 0x90000000	256M	PCI1 MEM Second half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 3:	256M	Non-cacheable, guarded
-	 * 0xa0000000	256M	PCI2 MEM First half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 4:	256M	Non-cacheable, guarded
-	 * 0xb0000000	256M	PCI2 MEM Second half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 5:	64M	Non-cacheable, guarded
-	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe200_0000	16M	PCI1 IO
-	 * 0xe300_0000	16M	PCI2 IO
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLB 6:	256M	Non-cacheable, guarded
-	 * 0xf0000000		Local bus expansion option.
-	 * 0xfb000000		Configuration Latch register (one word)
-	 * 0xfc000000		Up to 64M flash
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE, CONFIG_SYS_LBC_OPTION_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_256M, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/stxssa/u-boot.lds b/board/stxssa/u-boot.lds
deleted file mode 100644
index 750ddb3..0000000
--- a/board/stxssa/u-boot.lds
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * (C) Copyright 2005 Embedded Alley Solutions, Inc.
- * Dan Malek, <dan@embeddedalley.com>
- * Copied from STx GP3.
- * Updates for Silicon Tx GP3 SSA.
- *
- * (C) Copyright 2002,2003,Motorola,Inc.
- * Xianghua Xiao, X.Xiao@motorola.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  .resetvec 0xFFFFFFFC :
-  {
-    *(.resetvec)
-  } = 0xffff
-
-  .bootpg 0xFFFFF000 :
-  {
-    cpu/mpc85xx/start.o	(.bootpg)
-  } = 0xffff
-
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text)	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    cpu/mpc85xx/start.o	(.text)
-    cpu/mpc85xx/commproc.o (.text)
-    cpu/mpc85xx/traps.o (.text)
-    cpu/mpc85xx/interrupts.o (.text)
-    cpu/mpc85xx/serial_scc.o (.text)
-    cpu/mpc85xx/ether_fcc.o (.text)
-    cpu/mpc85xx/cpu_init.o (.text)
-    cpu/mpc85xx/cpu.o (.text)
-    cpu/mpc85xx/speed.o (.text)
-    common/dlmalloc.o (.text)
-    lib_generic/crc32.o (.text)
-    lib_ppc/extable.o (.text)
-    lib_generic/zlib.o (.text)
-    *(.text)
-    *(.fixup)
-    *(.got1)
-   }
-    _etext = .;
-    PROVIDE (etext = .);
-    .rodata    :
-   {
-    *(.eh_frame)
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
-  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  . = .;
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  _end = . ;
-  PROVIDE (end = .);
-}