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authorWolfgang Denk <wd@denx.de>2008-01-23 13:56:55 +0100
committerWolfgang Denk <wd@denx.de>2008-01-23 13:56:55 +0100
commit39166b5c9e7160761419f816f995b1d8029aa4a7 (patch)
tree45ec07fd02acb2338351b978194732af56c480a7 /board/stxssa
parentcfe5ca77976afdbe7ecb86e39fd7505bde636ace (diff)
parent6ea66a818de376ff599c40bdd6c361cfcba2fb6f (diff)
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Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
Diffstat (limited to 'board/stxssa')
-rw-r--r--board/stxssa/Makefile3
-rw-r--r--board/stxssa/init.S244
-rw-r--r--board/stxssa/law.c60
-rw-r--r--board/stxssa/tlb.c106
-rw-r--r--board/stxssa/u-boot.lds2
5 files changed, 167 insertions, 248 deletions
diff --git a/board/stxssa/Makefile b/board/stxssa/Makefile
index 344ecdf..f1f5d0b 100644
--- a/board/stxssa/Makefile
+++ b/board/stxssa/Makefile
@@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o
-SOBJS := init.o
+COBJS := $(BOARD).o law.o tlb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/stxssa/init.S b/board/stxssa/init.S
deleted file mode 100644
index 82dafb8..0000000
--- a/board/stxssa/init.S
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * Copyright (C) 2005 Embedded Alley Solutions, Inc.
- * Dan Malek <dan@embeddedalley.com>
- * Copied from STx GP3.
- * Updates for Silicon Tx GP3 SSA. We only support 32-bit flash
- * and DDR with SPD EEPROM configuration.
- *
- * Copyright 2004 Freescale Semiconductor.
- * Copyright (C) 2002,2003, Motorola Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <config.h>
-#include <mpc85xx.h>
-
-
-/*
- * TLB0 and TLB1 Entries
- *
- * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
- * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
- * these TLB entries are established.
- *
- * The TLB entries for DDR are dynamically setup in spd_sdram()
- * and use TLB1 Entries 8 through 15 as needed according to the
- * size of DDR memory.
- *
- * MAS0: tlbsel, esel, nv
- * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, x0, x1, w, i, m, g, e
- * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
- */
-
-#define entry_start \
- mflr r1 ; \
- bl 0f ;
-
-#define entry_end \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-
- .section .bootpg, "ax"
- .globl tlb1_entry
-tlb1_entry:
- entry_start
-
- /*
- * Number of TLB0 and TLB1 entries in the following table
- */
- .long 12
-
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
- /*
- * TLB0 4K Non-cacheable, guarded
- * 0xff700000 4K Initial CCSRBAR mapping
- *
- * This ends up at a TLB0 Index==0 entry, and must not collide
- * with other TLB0 Entries.
- */
- .long FSL_BOOKE_MAS0(0, 0, 0)
- .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
- .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
- .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-#else
-#error("Update the number of table entries in tlb1_entry")
-#endif
-
- /*
- * TLB0 16K Cacheable, non-guarded
- * 0xd001_0000 16K Temporary Global data for initialization
- *
- * Use four 4K TLB0 entries. These entries must be cacheable
- * as they provide the bootstrap memory before the memory
- * controler and real memory have been configured.
- *
- * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
- * and must not collide with other TLB0 entries.
- */
- .long FSL_BOOKE_MAS0(0, 0, 0)
- .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
- .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
- .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
- .long FSL_BOOKE_MAS0(0, 0, 0)
- .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
- .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
- .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
- .long FSL_BOOKE_MAS0(0, 0, 0)
- .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
- .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
- .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
- .long FSL_BOOKE_MAS0(0, 0, 0)
- .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
- .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
- .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-
- /*
- * TLB 0: 64M Non-cacheable, guarded
- * 0xfc000000 6M4 FLASH
- * Out of reset this entry is only 4K.
- */
- .long FSL_BOOKE_MAS0(1, 0, 0)
- .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
- .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
- /*
- * TLB 1: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM First half
- */
- .long FSL_BOOKE_MAS0(1, 1, 0)
- .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
- .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
- /*
- * TLB 2: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI1 MEM Second half
- */
- .long FSL_BOOKE_MAS0(1, 2, 0)
- .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
- .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
- /*
- * TLB 3: 256M Non-cacheable, guarded
- * 0xa0000000 256M PCI2 MEM First half
- */
- .long FSL_BOOKE_MAS0(1, 3, 0)
- .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G))
- .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
- /*
- * TLB 4: 256M Non-cacheable, guarded
- * 0xb0000000 256M PCI2 MEM Second half
- */
- .long FSL_BOOKE_MAS0(1, 4, 0)
- .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
- .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
- /*
- * TLB 5: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 16M PCI1 IO
- * 0xe300_0000 16M PCI2 IO
- */
- .long FSL_BOOKE_MAS0(1, 5, 0)
- .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
- .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
- /*
- * TLB 6: 256M Non-cacheable, guarded
- * 0xf0000000 Local bus expansion option.
- * 0xfb000000 Configuration Latch register (one word)
- * 0xfc000000 Up to 64M flash
- */
- .long FSL_BOOKE_MAS0(1, 7, 0)
- .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long FSL_BOOKE_MAS2(CFG_LBC_OPTION_BASE, (MAS2_I|MAS2_G))
- .long FSL_BOOKE_MAS3(CFG_LBC_OPTION_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
- entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
- * 0xf000_0000 0xfaff_ffff Local bus 128M
- * 0xfb00_0000 0xfb00_ffff Config Latch 64K
- * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-#if !defined(CONFIG_SPD_EEPROM)
-#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
-#else
-#define LAWBAR0 0
-#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-#endif
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
-
-#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
-
-/* Map the whole localbus, including flash and reset latch.
-*/
-#define LAWBAR5 ((CFG_LBC_OPTION_BASE>>12) & 0xfffff)
-#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-
- .section .bootpg, "ax"
- .globl law_entry
-law_entry:
- entry_start
- .long 6
- .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
- .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
- entry_end
diff --git a/board/stxssa/law.c b/board/stxssa/law.c
new file mode 100644
index 0000000..2b25292
--- /dev/null
+++ b/board/stxssa/law.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
+ * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
+ * 0xf000_0000 0xfaff_ffff Local bus 128M
+ * 0xfb00_0000 0xfb00_ffff Config Latch 64K
+ * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+ SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+#endif
+ SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+ SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
+ SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+ /* Map the whole localbus, including flash and reset latch. */
+ SET_LAW_ENTRY(6, CFG_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/stxssa/tlb.c b/board/stxssa/tlb.c
new file mode 100644
index 0000000..46b1440
--- /dev/null
+++ b/board/stxssa/tlb.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /*
+ * TLB 0: 64M Non-cacheable, guarded
+ * 0xfc000000 6M4 FLASH
+ * Out of reset this entry is only 4K.
+ */
+ SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ * 0xa0000000 256M PCI2 MEM First half
+ */
+ SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0xb0000000 256M PCI2 MEM Second half
+ */
+ SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 16M PCI1 IO
+ * 0xe300_0000 16M PCI2 IO
+ */
+ SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 6: 256M Non-cacheable, guarded
+ * 0xf0000000 Local bus expansion option.
+ * 0xfb000000 Configuration Latch register (one word)
+ * 0xfc000000 Up to 64M flash
+ */
+ SET_TLB_ENTRY(1, CFG_LBC_OPTION_BASE, CFG_LBC_OPTION_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_256M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/stxssa/u-boot.lds b/board/stxssa/u-boot.lds
index a0ba125..99a8a8b 100644
--- a/board/stxssa/u-boot.lds
+++ b/board/stxssa/u-boot.lds
@@ -40,7 +40,6 @@ SECTIONS
.bootpg 0xFFFFF000 :
{
cpu/mpc85xx/start.o (.bootpg)
- board/stxssa/init.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
@@ -70,7 +69,6 @@ SECTIONS
.text :
{
cpu/mpc85xx/start.o (.text)
- board/stxssa/init.o (.text)
cpu/mpc85xx/commproc.o (.text)
cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text)