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| author | Dave Liu <daveliu@freescale.com> | 2008-11-21 16:31:43 +0800 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2009-01-23 17:03:14 -0600 |
| commit | b4983e16d150ab7d039704c310aacbd2f4dc1e0f (patch) | |
| tree | e9d6b115e91cea5fe4e1ca3edc7d86bb28e4c190 /board/stxssa/ddr.c | |
| parent | 22cca7e1cd54590e967c73558b07ffbdccd39504 (diff) | |
| download | u-boot-imx-b4983e16d150ab7d039704c310aacbd2f4dc1e0f.zip u-boot-imx-b4983e16d150ab7d039704c310aacbd2f4dc1e0f.tar.gz u-boot-imx-b4983e16d150ab7d039704c310aacbd2f4dc1e0f.tar.bz2 | |
fsl-ddr: use the 1T timing as default configuration
For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/stxssa/ddr.c')
| -rw-r--r-- | board/stxssa/ddr.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/board/stxssa/ddr.c b/board/stxssa/ddr.c index 7850794..93d1100 100644 --- a/board/stxssa/ddr.c +++ b/board/stxssa/ddr.c @@ -65,6 +65,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, */ popts->write_data_delay = 3; + /* 2T timing enable */ + popts->twoT_en = 1; + /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed |