Patch by Jon Loeliger, 16 Jul 2004:

- support larger DDR memories up to 2G on the PC8540/8560ADS and
  STXGP3 boards
- Made MPC8540/8560ADS be 33Mhz PCI by default.
- Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
  and CONFIG_L2_INIT_RAM options.
- Refactor Local Bus initialization out of SDRAM setup.
- Re-implement new version of LBC11/DDR11 errata workarounds.
- Moved board specific PCI init parts out of CPU directory.
- Added TLB entry for PCI-1 IO Memory
- Updated README.mpc85xxads

1 files changed, 217 insertions, 84 deletions

diff --git a/board/stxgp3/init.S b/board/stxgp3/init.S
index 4953c0b..d504289 100644
--- a/board/stxgp3/init.S
+++ b/board/stxgp3/init.S
@@ -1,10 +1,11 @@
 /*
- * Copyright (C) 2003 Embedded Edge, LLC
+ * Copyright (C) 2004 Embedded Edge, LLC
  * Dan Malek <dan@embeddededge.com>
  * Copied from ADS85xx.
  * Updates for Silicon Tx GP3 8560.  We only support 32-bit flash
  * and DDR with SPD EEPROM configuration.
  *
+ * Copyright 2004 Freescale Semiconductor.
  * Copyright (C) 2002,2003, Motorola Inc.
  * Xianghua Xiao <X.Xiao@motorola.com>
  *
@@ -34,6 +35,24 @@
 #include <config.h>
 #include <mpc85xx.h>
 
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
 #define	entry_start \
 	mflr	r1 	;	\
 	bl	0f 	;
@@ -43,111 +62,225 @@
 	mtlr	r1	;	\
 	blr		;
 
-/* TLB1 entries configuration: */
 
 	.section	.bootpg, "ax"
 	.globl	tlb1_entry
 tlb1_entry:
 	entry_start
 
-		/* If RAMBOOT, we are testing and the BDI has set up
-		 * much of the MMU already.
-		 * TLB 4,5 SDRAM
-		 * TLB 15 is default CCSRBAR.
-		 */
-	.long 0x09	/* the following data table uses a few of 16 TLB entries */
-
-	.long TLB1_MAS0(1,1,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-
-	.long TLB1_MAS0(1,2,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
-	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-
-	.long TLB1_MAS0(1,3,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(((CFG_LBC_LCLDEVS_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_LBC_LCLDEVS_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-	.long TLB1_MAS0(1,4,0)
-	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
-
-	.long TLB1_MAS0(1,5,0)
-	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
-
-	.long TLB1_MAS0(1,6,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
-#if defined(CONFIG_RAM_AS_FLASH)
-	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-#else
-	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
-#endif
-	.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 13
 
-	.long TLB1_MAS0(1,7,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
-#ifdef CONFIG_L2_INIT_RAM
-	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
 #else
-	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+#error("Update the number of table entries in tlb1_entry")
 #endif
-	.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
 
-	.long TLB1_MAS0(1,8,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
-	.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), \
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), \
+			0,0,0,0,0,1,0,1,0,1)
 
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
-	.long TLB1_MAS0(1,15,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-#else
-	.long TLB1_MAS0(1,15,0)
-	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), \
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), \
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	Rapid IO MEM First half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	Rapid IO MEM Second half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), \
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), \
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 7:	16K	Non-cacheable, guarded
+	 * 0xfc000000	16K	Configuration Latch register
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64K)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+#if !defined(CONFIG_SPD_EEPROM)
+	/*
+	 * TLB 8, 9:	128M	DDR
+	 * 0x00000000	64M	DDR System memory
+	 * 0x04000000	64M	DDR System memory
+	 * Without SPD EEPROM configured DDR, this must be setup manually.
+	 * Make sure the TLB count at the top of this table is correct.
+	 * Likely it needs to be increased by two for these entries.
+	 */
+#error("Update the number of table entries in tlb1_entry")
+	.long TLB1_MAS0(1, 8, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1, 9, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+			0,0,0,0,0,1,0,1,0,1)
 #endif
+
 	entry_end
 
-/* LAW(Local Access Window) configuration:
- * 0000_0000-8000_0000: Up to 2G DDR
- * f000_0000-f3ff_ffff: PCI(256M)
- * f400_0000-f7ff_ffff: RapidIO(128M)
- * f800_0000-ffff_ffff: localbus(128M)
- *   f800_0000-fbff_ffff: LBC SDRAM(64M)
- *   fc00_0000-fcff_ffff: LBC BCSR (1M, Chip select 1)
- *   fdf0_0000-fdff_ffff: CCSRBAR(1M)
- *   ff00_0000-ffff_ffff: Flash(16M)
- * We don't need a local window for CCSRBAR and flash because they
- * reside in their default mapped spaces.
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xfc00_0000     0xfc00_ffff     Config Latch            64K
+ * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
  */
 
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
 #define LAWBAR0 0
-#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_2G)) & ~LAWAR_EN)
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
 
-#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1  (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
-#if !defined(CONFIG_RAM_AS_FLASH)
+/*
+ * This is not so much the SDRAM map as it is the whole localbus map.
+ */
 #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR2  (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
-#else
-#define LAWBAR2 0
-#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-#endif
+#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/*
+ * Rapid IO at 0xc000_0000 for 512 M
+ */
+#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR4	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
 
 	.section .bootpg, "ax"
-	.globl  law_entry
+	.globl	law_entry
 law_entry:
 	entry_start
-	.long 0x03
-	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
+	.long 0x05
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4
 	entry_end