Merge branch 'master' of git://www.denx.de/git/u-boot

8 files changed, 326 insertions, 35 deletions

diff --git a/board/socrates/Makefile b/board/socrates/Makefile
index 6453f24..a41fead 100644
--- a/board/socrates/Makefile
+++ b/board/socrates/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 #
 
-COBJS	:= $(BOARD).o law.o tlb.o sdram.o
+COBJS	:= $(BOARD).o law.o tlb.o sdram.o nand.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
@@ -41,7 +41,7 @@ clean:
 	rm -f $(OBJS) $(SOBJS)
 
 distclean:	clean
-	rm -f $(LIB) core *.bak .depend
+	rm -f $(LIB) core *.bak $(obj).depend
 
 #########################################################################
 
diff --git a/board/socrates/config.mk b/board/socrates/config.mk
index 1cf5d38..4f17294 100644
--- a/board/socrates/config.mk
+++ b/board/socrates/config.mk
@@ -25,6 +25,5 @@
 #
 # socrates board
 # default CCARBAR is at 0xff700000
-# assume U-Boot is less than 256k
 #
-TEXT_BASE = 0xfffc0000
+TEXT_BASE = 0xfffa0000
diff --git a/board/socrates/law.c b/board/socrates/law.c
index 5f4b8ca..35c4a90 100644
--- a/board/socrates/law.c
+++ b/board/socrates/law.c
@@ -33,13 +33,12 @@
 /*
  * LAW(Local Access Window) configuration:
  *
- * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
+ * 0x0000_0000	   0x2fff_ffff	   DDR			   512M
  * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
- * 0xc000_0000	   0xdfff_ffff	   RapidIO		   512M
- * 0xe000_0000	   0xe000_ffff	   CCSR			   1M
+ * 0xc000_0000	   0xc00f_ffff	   FPGA			   1M
+ * 0xe000_0000	   0xe00f_ffff	   CCSR			   1M (mapped by CCSRBAR)
  * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
- * 0xf800_0000	   0xf80f_ffff	   BCSR			   1M
- * 0xfe00_0000	   0xffff_ffff	   FLASH (boot bank)	   32M
+ * 0xfc00_0000	   0xffff_ffff	   FLASH		   64M
  *
  * Notes:
  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
@@ -47,11 +46,13 @@
  */
 
 struct law_entry law_table[] = {
-	SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
-	SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
-	SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
-	SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+#if defined(CFG_FPGA_BASE)
+	SET_LAW(CFG_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/socrates/nand.c b/board/socrates/nand.c
new file mode 100644
index 0000000..fc82ecb
--- /dev/null
+++ b/board/socrates/nand.c
@@ -0,0 +1,218 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CFG_NAND_BASE)
+#include <nand.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+
+static int state;
+static void nand_write_byte(struct mtd_info *mtd, u_char byte);
+static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
+static void nand_write_word(struct mtd_info *mtd, u16 word);
+static u_char nand_read_byte(struct mtd_info *mtd);
+static u16 nand_read_word(struct mtd_info *mtd);
+static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
+static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
+static int nand_device_ready(struct mtd_info *mtdinfo);
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd);
+
+#define FPGA_NAND_CMD_MASK		(0x7 << 28)
+#define FPGA_NAND_CMD_COMMAND	(0x0 << 28)
+#define FPGA_NAND_CMD_ADDR		(0x1 << 28)
+#define FPGA_NAND_CMD_READ		(0x2 << 28)
+#define FPGA_NAND_CMD_WRITE		(0x3 << 28)
+#define FPGA_NAND_BUSY			(0x1 << 15)
+#define FPGA_NAND_ENABLE		(0x1 << 31)
+#define FPGA_NAND_DATA_SHIFT	16
+
+/**
+ * nand_write_byte -  write one byte to the chip
+ * @mtd:	MTD device structure
+ * @byte:	pointer to data byte to write
+ */
+static void nand_write_byte(struct mtd_info *mtd, u_char byte)
+{
+	nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte));
+}
+
+/**
+ * nand_write_word -  write one word to the chip
+ * @mtd:	MTD device structure
+ * @word:	data word to write
+ */
+static void nand_write_word(struct mtd_info *mtd, u16 word)
+{
+	nand_write_buf(mtd, (const uchar *)&word, sizeof(word));
+}
+
+/**
+ * nand_write_buf -  write buffer to chip
+ * @mtd:	MTD device structure
+ * @buf:	data buffer
+ * @len:	number of bytes to write
+ */
+static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	int i;
+	struct nand_chip *this = mtd->priv;
+	long val;
+
+	if ((state & FPGA_NAND_CMD_MASK) == FPGA_NAND_CMD_MASK) {
+		/* Write data */
+		val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_WRITE;
+	} else {
+		/* Write address or command */
+		val = state;
+	}
+
+	for (i = 0; i < len; i++) {
+		out_be32(this->IO_ADDR_W, val | (buf[i] << FPGA_NAND_DATA_SHIFT));
+	}
+}
+
+
+/**
+ * nand_read_byte -  read one byte from the chip
+ * @mtd:	MTD device structure
+ */
+static u_char nand_read_byte(struct mtd_info *mtd)
+{
+	u8 byte;
+	nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
+	return byte;
+}
+
+/**
+ * nand_read_word -  read one word from the chip
+ * @mtd:	MTD device structure
+ */
+static u16 nand_read_word(struct mtd_info *mtd)
+{
+	u16 word;
+	nand_read_buf(mtd, (uchar *)&word, sizeof(word));
+	return word;
+}
+
+/**
+ * nand_read_buf -  read chip data into buffer
+ * @mtd:	MTD device structure
+ * @buf:	buffer to store date
+ * @len:	number of bytes to read
+ */
+static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+	int i;
+	struct nand_chip *this = mtd->priv;
+	int val;
+
+	val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ;
+
+	out_be32(this->IO_ADDR_W, val);
+	for (i = 0; i < len; i++) {
+		buf[i] = (in_be32(this->IO_ADDR_R) >> FPGA_NAND_DATA_SHIFT) & 0xff;
+	}
+}
+
+/**
+ * nand_verify_buf -  Verify chip data against buffer
+ * @mtd:	MTD device structure
+ * @buf:	buffer containing the data to compare
+ * @len:	number of bytes to compare
+ */
+static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++) {
+		if (buf[i] != nand_read_byte(mtd));
+		return -EFAULT;
+	}
+	return 0;
+}
+
+/**
+ * nand_device_ready - Check the NAND device is ready for next command.
+ * @mtd:	MTD device structure
+ */
+static int nand_device_ready(struct mtd_info *mtdinfo)
+{
+	struct nand_chip *this = mtdinfo->priv;
+
+	if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY)
+		return 0; /* busy */
+	return 1;
+}
+
+/**
+ * nand_hwcontrol - NAND control functions wrapper.
+ * @mtd:	MTD device structure
+ * @cmd:	Command
+ */
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+
+	switch(cmd) {
+	case NAND_CTL_CLRALE:
+		state |= FPGA_NAND_CMD_MASK; /* use all 1s to mark */
+		break;
+	case NAND_CTL_CLRCLE:
+		state |= FPGA_NAND_CMD_MASK; /* use all 1s to mark */
+		break;
+	case NAND_CTL_SETCLE:
+		state = (state & ~FPGA_NAND_CMD_MASK) | FPGA_NAND_CMD_COMMAND;
+		break;
+	case NAND_CTL_SETALE:
+		state = (state & ~FPGA_NAND_CMD_MASK) | FPGA_NAND_CMD_ADDR;
+		break;
+	case NAND_CTL_SETNCE:
+		state |= FPGA_NAND_ENABLE;
+		break;
+	case NAND_CTL_CLRNCE:
+		state &= ~FPGA_NAND_ENABLE;
+		break;
+	default:
+		printf("%s: unknown cmd %#x\n", __FUNCTION__, cmd);
+		break;
+	}
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->hwcontrol = nand_hwcontrol;
+	nand->eccmode = NAND_ECC_SOFT;
+	nand->dev_ready = nand_device_ready;
+	nand->write_byte = nand_write_byte;
+	nand->read_byte = nand_read_byte;
+	nand->write_word = nand_write_word;
+	nand->read_word = nand_read_word;
+	nand->write_buf = nand_write_buf;
+	nand->read_buf = nand_read_buf;
+	nand->verify_buf = nand_verify_buf;
+
+	return 0;
+}
+
+#endif
diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c
index 329eacc..768fe05 100644
--- a/board/socrates/sdram.c
+++ b/board/socrates/sdram.c
@@ -76,7 +76,7 @@ long int sdram_setup(int casl)
 }
 #endif
 
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
 	long dram_size = 0;
 #if defined(CONFIG_SPD_EEPROM)
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index cb58994..d791f11 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -35,7 +35,11 @@
 #include <flash.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <asm/io.h>
 
+#if defined(CFG_FPGA_BASE)
+#include "upm_table.h"
+#endif
 DECLARE_GLOBAL_DATA_PTR;
 
 extern flash_info_t flash_info[];	/* FLASH chips info */
@@ -45,6 +49,9 @@ ulong flash_get_size (ulong base, int banknum);
 
 int checkboard (void)
 {
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	char *src;
+	int f;
 	char *s = getenv("serial#");
 
 	puts("Board: Socrates");
@@ -55,8 +62,15 @@ int checkboard (void)
 	putc('\n');
 
 #ifdef CONFIG_PCI
-	printf ("PCI1:  32 bit, %d MHz (compiled)\n",
-		CONFIG_SYS_CLK_FREQ / 1000000);
+	/* Check the PCI_clk sel bit */
+	if (in_be32(&gur->porpllsr) & (1<<15)) {
+		src = "SYSCLK";
+		f = CONFIG_SYS_CLK_FREQ;
+	} else {
+		src = "PCI_CLK";
+		f = CONFIG_PCI_CLK_FREQ;
+	}
+	printf ("PCI1:  32 bit, %d MHz (%s)\n",	f/1000000, src);
 #else
 	printf ("PCI1:  disabled\n");
 #endif
@@ -65,7 +79,10 @@ int checkboard (void)
 	 * Initialize local bus.
 	 */
 	local_bus_init ();
-
+#if defined(CFG_FPGA_BASE)
+	/* Init UPMA for FPGA access */
+	upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
+#endif
 	return 0;
 }
 
@@ -207,5 +224,15 @@ ft_board_setup(void *blob, bd_t *bd)
 	if (rc)
 		printf("Unable to update property NOR mapping, err=%s\n",
 		       fdt_strerror(rc));
+
+#if defined (CFG_FPGA_BASE)
+	memset(val, 0, sizeof(val));
+	val[0] = CFG_FPGA_BASE;
+	rc = fdt_find_and_setprop(blob, "/localbus/fpga", "virtual-reg",
+				  val, sizeof(val), 1);
+	if (rc)
+		printf("Unable to update property \"fpga\", err=%s\n",
+		       fdt_strerror(rc));
+#endif
 }
 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c
index b80caea..aea99ad 100644
--- a/board/socrates/tlb.c
+++ b/board/socrates/tlb.c
@@ -46,16 +46,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 
 	/*
-	 * TLB 0, 1:	128M	Non-cacheable, guarded
-	 * 0xf8000000	128M	FLASH
+	 * TLB 0:	64M	Non-cacheable, guarded
+	 * 0xfc000000	64M	FLASH
 	 * Out of reset this entry is only 4K.
 	 */
 	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_64M, 1),
-	SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_64M, 1),
 
 	/*
 	 * TLB 2:	256M	Non-cacheable, guarded
@@ -73,21 +70,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
+#if defined(CFG_FPGA_BASE)
 	/*
-	 * TLB 4:	256M	Non-cacheable, guarded
-	 * 0xc0000000	256M	Rapid IO MEM First half
-	 */
-	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 5:	256M	Non-cacheable, guarded
-	 * 0xd0000000	256M	Rapid IO MEM Second half
+	 * TLB 4:	1M	Non-cacheable, guarded
+	 * 0xc0000000	1M	FPGA and NAND
 	 */
-	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY(1, CFG_FPGA_BASE, CFG_FPGA_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_256M, 1),
+		      0, 4, BOOKE_PAGESZ_1M, 1),
+#endif
 
 	/*
 	 * TLB 6:	64M	Non-cacheable, guarded
diff --git a/board/socrates/upm_table.h b/board/socrates/upm_table.h
new file mode 100644
index 0000000..ea64a59
--- /dev/null
+++ b/board/socrates/upm_table.h
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Copyright 2004, 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __UPM_TABLE_H
+#define __UPM_TABLE_H
+
+/* UPM Table Configuration Code for FPGA access */
+static const unsigned int UPMTableA[] =
+{
+	0x00fcfc00,  0x00fcfc00,  0x00fcfc00,  0x00fcfc00, /* Words  0 to  3 */
+	0x00fcfc00,  0x00fcfc00,  0x00fcfc00,  0x00fcfc05, /* Words  4 to  7 */
+	0x00fcfc00,  0x00fcfc00,  0x00fcfc04,  0x00fcfc04, /* Words  8 to 11 */
+	0x00fcfc04,  0x00fcfc04,  0x00fcfc04,  0x00fcfc04, /* Words 12 to 15 */
+	0x00fcfc04,  0x00fcfc04,  0x00fcfc00,  0xfffffc00, /* Words 16 to 19 */
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, /* Words 20 to 23 */
+	0x0ffffc00,  0x0ffffc00,  0x0ffffc00,  0x00f3fc04, /* Words 24 to 27 */
+	0x0ffffc00,  0xfffffc01,  0xfffffc00,  0xfffffc01, /* Words 28 to 31 */
+	0x0ffffc00,  0x00f3fc04,  0x00f3fc04,  0x00f3fc04, /* Words 32 to 35 */
+	0x00f3fc04,  0x00f3fc04,  0x00f3fc04,  0x00f3fc04, /* Words 36 to 39 */
+	0x00f3fc04,  0x0ffffc00,  0xfffffc00,  0xfffffc00, /* Words 40 to 43 */
+	0xfffffc01,  0xfffffc00,  0xfffffc00,  0xfffffc01, /* Words 44 to 47 */
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 48 to 51 */
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 52 to 55 */
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, /* Words 56 to 59 */
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01  /* Words 60 to 63 */
+};
+
+#endif