diff options
author | Markus Klotzbuecher <mk@denx.de> | 2008-10-21 09:18:01 +0200 |
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committer | Markus Klotzbuecher <mk@denx.de> | 2008-10-21 09:18:01 +0200 |
commit | 50bd0057ba8fceeb48533f8b1a652ccd0e170838 (patch) | |
tree | ea1a183343573c2a48248923b96d316c0956727c /board/socrates/socrates.c | |
parent | 9dbc366744960013965fce8851035b6141f3b3ae (diff) | |
parent | f82642e33899766892499b163e60560fbbf87773 (diff) | |
download | u-boot-imx-50bd0057ba8fceeb48533f8b1a652ccd0e170838.zip u-boot-imx-50bd0057ba8fceeb48533f8b1a652ccd0e170838.tar.gz u-boot-imx-50bd0057ba8fceeb48533f8b1a652ccd0e170838.tar.bz2 |
Merge git://git.denx.de/u-boot into x1
Conflicts:
drivers/usb/usb_ohci.c
Diffstat (limited to 'board/socrates/socrates.c')
-rw-r--r-- | board/socrates/socrates.c | 118 |
1 files changed, 59 insertions, 59 deletions
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 0991177..d83dc7d 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -51,7 +51,7 @@ ulong flash_get_size (ulong base, int banknum); int checkboard (void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); char *src; int f; @@ -87,7 +87,7 @@ int checkboard (void) int misc_init_r (void) { - volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); /* * Adjust flash start and offset to detected values @@ -98,20 +98,20 @@ int misc_init_r (void) /* * Check if boot FLASH isn't max size */ - if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) { - memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff); - memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff); + if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) { + memctl->or0 = gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff); + memctl->br0 = gd->bd->bi_flashstart | (CONFIG_SYS_BR0_PRELIM & 0x00007fff); /* * Re-check to get correct base address */ - flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); + flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1); } /* * Check if only one FLASH bank is available */ - if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) { + if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { memctl->or1 = 0; memctl->br1 = 0; @@ -120,24 +120,24 @@ int misc_init_r (void) */ flash_protect (FLAG_PROTECT_CLEAR, gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, CONFIG_ENV_ADDR, CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Redundant environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); } return 0; @@ -148,12 +148,12 @@ int misc_init_r (void) */ void local_bus_init (void) { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); sys_info_t sysinfo; uint clkdiv; uint lbc_mhz; - uint lcrr = CFG_LBC_LCRR; + uint lcrr = CONFIG_SYS_LBC_LCRR; get_sys_info (&sysinfo); clkdiv = lbc->lcrr & 0x0f; @@ -219,7 +219,7 @@ void pci_init_board (void) #ifdef CONFIG_BOARD_EARLY_INIT_R int board_early_init_r (void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); /* set and reset the GPIO pin 2 which will reset the W83782G chip */ out_8((unsigned char*)&gur->gpoutdr, 0x3F ); @@ -246,19 +246,19 @@ ft_board_setup(void *blob, bd_t *bd) val[i++] = gd->bd->bi_flashstart; val[i++] = gd->bd->bi_flashsize; - if (mb862xx.frameAdrs == CFG_LIME_BASE) { + if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) { /* Fixup LIME mapping */ val[i++] = 2; /* chip select number */ val[i++] = 0; /* always 0 */ - val[i++] = CFG_LIME_BASE; - val[i++] = CFG_LIME_SIZE; + val[i++] = CONFIG_SYS_LIME_BASE; + val[i++] = CONFIG_SYS_LIME_SIZE; } /* Fixup FPGA mapping */ val[i++] = 3; /* chip select number */ val[i++] = 0; /* always 0 */ - val[i++] = CFG_FPGA_BASE; - val[i++] = CFG_FPGA_SIZE; + val[i++] = CONFIG_SYS_FPGA_BASE; + val[i++] = CONFIG_SYS_FPGA_SIZE; rc = fdt_find_and_setprop(blob, "/localbus", "ranges", val, i * sizeof(u32), 1); @@ -268,14 +268,14 @@ ft_board_setup(void *blob, bd_t *bd) } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ -#define CFG_LIME_SRST ((CFG_LIME_BASE) + 0x01FC002C) -#define CFG_LIME_CCF ((CFG_LIME_BASE) + 0x01FC0038) -#define CFG_LIME_MMR ((CFG_LIME_BASE) + 0x01FCFFFC) +#define CONFIG_SYS_LIME_SRST ((CONFIG_SYS_LIME_BASE) + 0x01FC002C) +#define CONFIG_SYS_LIME_CCF ((CONFIG_SYS_LIME_BASE) + 0x01FC0038) +#define CONFIG_SYS_LIME_MMR ((CONFIG_SYS_LIME_BASE) + 0x01FCFFFC) /* Lime clock frequency */ -#define CFG_LIME_CLK_100MHZ 0x00000 -#define CFG_LIME_CLK_133MHZ 0x10000 +#define CONFIG_SYS_LIME_CLK_100MHZ 0x00000 +#define CONFIG_SYS_LIME_CLK_133MHZ 0x10000 /* SDRAM parameter */ -#define CFG_LIME_MMR_VALUE 0x4157BA63 +#define CONFIG_SYS_LIME_MMR_VALUE 0x4157BA63 #define DISPLAY_WIDTH 800 #define DISPLAY_HEIGHT 480 @@ -308,11 +308,11 @@ const gdc_regs *board_get_regs (void) return init_regs; } -#define CFG_LIME_CID ((CFG_LIME_BASE) + 0x01FC00F0) -#define CFG_LIME_REV ((CFG_LIME_BASE) + 0x01FF8084) +#define CONFIG_SYS_LIME_CID ((CONFIG_SYS_LIME_BASE) + 0x01FC00F0) +#define CONFIG_SYS_LIME_REV ((CONFIG_SYS_LIME_BASE) + 0x01FF8084) int lime_probe(void) { - volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint cfg_br2; uint cfg_or2; uint reg; @@ -323,14 +323,14 @@ int lime_probe(void) /* Configure GPCM for CS2 */ memctl->br2 = 0; memctl->or2 = 0xfc000410; - memctl->br2 = (CFG_LIME_BASE) | 0x00001901; + memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901; /* Try to access GDC ID/Revision registers */ - reg = in_be32((void *)CFG_LIME_CID); - reg = in_be32((void *)CFG_LIME_CID); + reg = in_be32((void *)CONFIG_SYS_LIME_CID); + reg = in_be32((void *)CONFIG_SYS_LIME_CID); if (reg == 0x303) { - reg = in_be32((void *)CFG_LIME_REV); - reg = in_be32((void *)CFG_LIME_REV); + reg = in_be32((void *)CONFIG_SYS_LIME_REV); + reg = in_be32((void *)CONFIG_SYS_LIME_REV); reg = ((reg & ~0xff) == 0x20050100) ? 1 : 0; } else reg = 0; @@ -351,22 +351,22 @@ unsigned int board_video_init (void) /* * Reset Lime controller */ - out_be32((void *)CFG_LIME_SRST, 0x1); + out_be32((void *)CONFIG_SYS_LIME_SRST, 0x1); udelay(200); /* Set Lime clock to 133MHz */ - out_be32((void *)CFG_LIME_CCF, CFG_LIME_CLK_133MHZ); + out_be32((void *)CONFIG_SYS_LIME_CCF, CONFIG_SYS_LIME_CLK_133MHZ); /* Delay required */ udelay(300); /* Set memory parameters */ - out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE); + out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE); mb862xx.winSizeX = DISPLAY_WIDTH; mb862xx.winSizeY = DISPLAY_HEIGHT; mb862xx.gdfIndex = GDF_15BIT_555RGB; mb862xx.gdfBytesPP = 2; - return CFG_LIME_BASE; + return CONFIG_SYS_LIME_BASE; } #define W83782D_REG_CFG 0x40 @@ -381,22 +381,22 @@ static int w83782d_hwmon_init(void) { u8 buf; - if (i2c_read(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1)) + if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1)) return -1; - i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80); - i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0); - i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40); - buf = i2c_reg_read(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL); - i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL, + buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL, buf | 0x80); - i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0); - i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47); - i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01); - buf = i2c_reg_read(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG); - i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG, + buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, (buf & 0xf4) | 0x01); return 0; } @@ -408,37 +408,37 @@ static void board_backlight_brightness(int br) u8 old_buf; /* Select bank 0 */ - if (i2c_read(CFG_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) + if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) goto err; else buf = old_buf & 0xf8; - if (i2c_write(CFG_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1)) + if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1)) goto err; if (br > 0) { /* PWMOUT1 duty cycle ctrl */ buf = 255 / (100 / br); - if (i2c_write(CFG_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) + if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) goto err; /* LEDs on */ - reg = in_be32((void *)(CFG_FPGA_BASE + 0x0c)); + reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); if (!(reg & BACKLIGHT_ENABLE)); - out_be32((void *)(CFG_FPGA_BASE + 0x0c), + out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg | BACKLIGHT_ENABLE); } else { buf = 0; - if (i2c_write(CFG_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) + if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) goto err; /* LEDs off */ - reg = in_be32((void *)(CFG_FPGA_BASE + 0x0c)); + reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); reg &= ~BACKLIGHT_ENABLE; - out_be32((void *)(CFG_FPGA_BASE + 0x0c), reg); + out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg); } /* Restore previous bank setting */ - if (i2c_write(CFG_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) + if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) goto err; return; |