am335x: Initial support for Silica Pengwyn board

This patch add support for the Silica Pengwyn board [1]
The board is based on a TI AM3354 CPU [2]
All jumpers removed it will boot from the SDcard, the console is on
UART1 accessible via the FDTI -> USB. The on board NAND flash is
supported and can act as boot medium, depending on jumper settings.
USB Host, USB Device and Ethernet are also provided but untested.

[1]
http://www.silica.com/product/silica-pengwyn-board.html
[2]
http://www.ti.com/product/am3354

Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
[trini: Move CONFIG_BOARD_LATE_INIT into am335x_evm.h, drop unused
spi0_pin_mux from Pengwyn support]
Signed-off-by: Tom Rini <trini@ti.com>

4 files changed, 333 insertions, 0 deletions

diff --git a/board/silica/pengwyn/Makefile b/board/silica/pengwyn/Makefile
new file mode 100644
index 0000000..c8b4f9a
--- /dev/null
+++ b/board/silica/pengwyn/Makefile
@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o
diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c
new file mode 100644
index 0000000..a553129
--- /dev/null
+++ b/board/silica/pengwyn/board.c
@@ -0,0 +1,207 @@
+/*
+ * board.c
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <phy.h>
+#include <cpsw.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#if defined(CONFIG_SPL_BUILD)
+
+/* DDR3 RAM timings */
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K128MJT187E_RD_DQS,
+	.datawdsratio0 = MT41K128MJT187E_WR_DQS,
+	.datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K128MJT187E_RATIO,
+	.cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT,
+	.cmd1csratio = MT41K128MJT187E_RATIO,
+	.cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT,
+	.cmd2csratio = MT41K128MJT187E_RATIO,
+	.cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K128MJT187E_EMIF_SDCFG,
+	.ref_ctrl = MT41K128MJT187E_EMIF_SDREF,
+	.sdram_tim1 = MT41K128MJT187E_EMIF_TIM1,
+	.sdram_tim2 = MT41K128MJT187E_EMIF_TIM2,
+	.sdram_tim3 = MT41K128MJT187E_EMIF_TIM3,
+	.zq_config = MT41K128MJT187E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
+};
+
+const struct ctrl_ioregs ddr3_ioregs = {
+	.cm0ioctl		= MT41K128MJT187E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K128MJT187E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K128MJT187E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K128MJT187E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K128MJT187E_IOCTRL_VALUE,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+#define OSC	(V_OSCK/1000000)
+const struct dpll_params dpll_ddr_266 = {
+		266, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_303 = {
+		303, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_400 = {
+		400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	/*
+	 * The pengwyn board uses the TPS650250 PMIC  without I2C
+	 * interface and will output the following fixed voltages:
+	 * DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu)
+	 * VLDO1=1V8 (IO) VLDO2=1V8(IO)
+	 * Vcore=1V1 is fixed, generated by TPS62231
+	 */
+
+	/* Get the frequency */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* 720MHz cpu, this might change on newer board revisions */
+	dpll_mpu_opp100.m = MPUPLL_M_720;
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	/* future configs can return other clock settings */
+	return &dpll_ddr_303;
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+void sdram_init(void)
+{
+	config_ddr(303, &ddr3_ioregs, &ddr3_data,
+		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#endif /* if CONFIG_SPL_BUILD */
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gpmc_init();
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_id		= 0,
+		.phy_if		= PHY_INTERFACE_MODE_MII,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_id		= 1,
+		.phy_if		= PHY_INTERFACE_MODE_MII,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+	int rv, n = 0;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+		printf("<ethaddr> not set. Reading from E-fuse\n");
+		/* try reading mac address from efuse */
+		mac_lo = readl(&cdev->macid0l);
+		mac_hi = readl(&cdev->macid0h);
+		mac_addr[0] = mac_hi & 0xFF;
+		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+		mac_addr[4] = mac_lo & 0xFF;
+		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+		else
+			return n;
+	}
+
+	writel(MII_MODE_ENABLE, &cdev->miisel);
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+	return n;
+}
+#endif /* if CONFIG_DRIVER_TI_CPSW */
diff --git a/board/silica/pengwyn/board.h b/board/silica/pengwyn/board.h
new file mode 100644
index 0000000..05addf6
--- /dev/null
+++ b/board/silica/pengwyn/board.h
@@ -0,0 +1,15 @@
+/*
+ * board.h
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+
+#endif
diff --git a/board/silica/pengwyn/mux.c b/board/silica/pengwyn/mux.c
new file mode 100644
index 0000000..c8be440
--- /dev/null
+++ b/board/silica/pengwyn/mux.c
@@ -0,0 +1,98 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+/* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+/* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */
+
+/* I2C pins C16(scl)/C17(sda) */
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+					PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+					PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */
+	{-1},
+};
+
+/* MMC0 pins */
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_CMD */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},  /* MMC0_CD */
+	{-1},
+};
+
+/* MII pins */
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
+	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
+	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
+	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+/* NAND pins */
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_board_pin_mux()
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(uart0_pin_mux);
+	configure_module_pin_mux(mii1_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(nand_pin_mux);
+}