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author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-12-10 15:02:21 +0530 |
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committer | Tom Rini <trini@ti.com> | 2013-12-18 21:14:18 -0500 |
commit | 965de8b91bddd1f5967240d1d44005719b09dd5e (patch) | |
tree | dbcbdffdaaf14e8ace3eb1a911f27ace0352bbc6 /board/siemens/dxr2 | |
parent | cf04d0326bd1e24909cfe644c0c8676440a915b1 (diff) | |
download | u-boot-imx-965de8b91bddd1f5967240d1d44005719b09dd5e.zip u-boot-imx-965de8b91bddd1f5967240d1d44005719b09dd5e.tar.gz u-boot-imx-965de8b91bddd1f5967240d1d44005719b09dd5e.tar.bz2 |
ARM: AM33xx+: Update ioregs to pass different values
Currently same value is programmed for all ioregs. This is not
the case for all SoC's like AM4372. So adding a structure for ioregs
and updating in all board files. And also return from config_cmd_ctrl()
and config_ddr_data() functions if data is not passed.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Fixup dxr2, cm_t335, adapt pcm051 rev3]
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'board/siemens/dxr2')
-rw-r--r-- | board/siemens/dxr2/board.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c index 3a5e11d..6c316fa 100644 --- a/board/siemens/dxr2/board.c +++ b/board/siemens/dxr2/board.c @@ -144,6 +144,10 @@ struct ddr_data dxr2_ddr3_data = { struct cmd_control dxr2_ddr3_cmd_ctrl_data = { }; + +struct ctrl_ioregs dxr2_ddr3_ioregs = { +}; + /* pass values from eeprom */ dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1; dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2; @@ -165,7 +169,13 @@ struct cmd_control dxr2_ddr3_cmd_ctrl_data = { dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio; dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout; - config_ddr(DDR_PLL_FREQ, settings.ddr3.ioctr_val, &dxr2_ddr3_data, + dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val, + dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val, + dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val, + dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val, + dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val, + + config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data, &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0); } |