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authorSamuel Egli <samuel.egli@siemens.com>2013-11-04 14:05:03 +0100
committerTom Rini <trini@ti.com>2013-11-12 09:53:59 -0500
commit56eb3da43fab5990a4b7bc118b76c7cae2ceb140 (patch)
tree46ba8b1bf05596d48fa247f7a2a89450509be5b3 /board/siemens/dxr2
parent7a0d463f587b0c00f6abfd33d96fae9fdd0dc55a (diff)
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arm, am335x: update for the siemens boards
- dxr2: define unused pins as input - do not enable RTC32K OSC on dxr2 board - update default environment - add splashpos=m,m to default environment, so splash screen is always centered. - adapt environment for bootcount feature - add altbootcmd to default environment - rut: SPL add early reset pulse for eth-phy, maXTouch and display - rut: display timing aenderungen - siemens boards: adapt for background color = white - add boutcount feature for the siemens boards store the bootcount in the environment, as we have no softreset save registers on this hardware. Use therefore the CONFIG_BOOTCOUNT_ENV bootcount driver. - change spi mode from 3 to 0 for the lcd init - add gpio pin for lcd reset with state 0 and add mdelay - siemens boards: use own USB id's - add dfu serial and device number for siemens boards Add for the siemens boards the possibility to define in dfu mode, the iSerialNumber and the bcdDevice fields in the USB Device descriptor. - fix upgrade mechanism based on bootcount Correct location of saveenv and remove not active variable. Add CONFIG_BOOT_RETRY_TIME and CONFIG_RESET_TO_RETRY to reboot board in case of empty kernel partition. Without these defines an empty kernel partition leads to an abort of boot process and one remains in u-boot prompt. - general cleanup of dxr2, pxm2 and rut boards all: * Remove net boot from bootcmd Ping can cause a crash on boards without ethernet phy. net_nfs command is used only for development * Add reset at the end of bootcmd In order to have an immediate reset of the boot when bootcmd fails, add reset at the end of bootcmd. rut: * add nand_img_size dxr2: * update nand_img_size * ddr3 timings updated with iocontrol property that can be modified via eeprom. New default parameters from software leveling with draco ES2. Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Signed-off-by: Pascal Bach <pascal.bach@siemens.com> Signed-off-by: Roger Meier <r.meier@siemens.com> Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Matthias Michel <matthias.michel@siemens.com> Cc: Tom Rini <trini@ti.com>
Diffstat (limited to 'board/siemens/dxr2')
-rw-r--r--board/siemens/dxr2/board.c11
-rw-r--r--board/siemens/dxr2/board.h9
-rw-r--r--board/siemens/dxr2/mux.c158
3 files changed, 169 insertions, 9 deletions
diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c
index af9d84f..1773ab7 100644
--- a/board/siemens/dxr2/board.c
+++ b/board/siemens/dxr2/board.c
@@ -38,11 +38,11 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD
static struct dxr2_baseboard_id __attribute__((section(".data"))) settings;
-
+/* @303MHz-i0 */
const struct ddr3_data ddr3_default = {
- 0x33524444, 0x56312e33, 0x0100, 0x0001, 0x003A, 0x008A, 0x010B,
- 0x00C4, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x0006, 0x61C04AB2,
- 0x00000618,
+ 0x33524444, 0x56312e34, 0x0080, 0x0000, 0x0038, 0x003E, 0x00A4,
+ 0x0075, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
+ 0x00000618, 0x0000014A,
};
static void set_default_ddr3_timings(void)
@@ -73,6 +73,7 @@ static void print_ddr3_timings(void)
PRINTARGS(sdram_config);
PRINTARGS(ref_ctrl);
+ PRINTARGS(ioctr_val);
}
static void print_chip_data(void)
@@ -168,7 +169,7 @@ struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
- config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &dxr2_ddr3_data,
+ config_ddr(DDR_PLL_FREQ, settings.ddr3.ioctr_val, &dxr2_ddr3_data,
&dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
}
diff --git a/board/siemens/dxr2/board.h b/board/siemens/dxr2/board.h
index 2be78fb..abf5432 100644
--- a/board/siemens/dxr2/board.h
+++ b/board/siemens/dxr2/board.h
@@ -22,11 +22,11 @@
#define MAGIC_CHIP 0x50494843
/* Automatic generated definition */
-/* Wed, 19 Jun 2013 10:57:48 +0200 */
-/* From file: draco/ddr3-data-micron.txt */
+/* Wed, 18 Sep 2013 18:58:27 +0200 */
+/* From file: draco/ddr3-data-micron-v2.txt */
struct ddr3_data {
unsigned int magic; /* 0x33524444 */
- unsigned int version; /* 0x56312e33 */
+ unsigned int version; /* 0x56312e34 */
unsigned short int ddr3_sratio; /* 0x0100 */
unsigned short int iclkout; /* 0x0001 */
unsigned short int dt0rdsratio0; /* 0x003A */
@@ -36,9 +36,10 @@ struct ddr3_data {
unsigned int sdram_tim1; /* 0x0888A39B */
unsigned int sdram_tim2; /* 0x26247FDA */
unsigned int sdram_tim3; /* 0x501F821F */
- unsigned short int emif_ddr_phy_ctlr_1; /* 0x0006 */
+ unsigned int emif_ddr_phy_ctlr_1; /* 0x00100206 */
unsigned int sdram_config; /* 0x61C04AB2 */
unsigned int ref_ctrl; /* 0x00000618 */
+ unsigned int ioctr_val; /* 0x0000018B */
};
struct chip_data {
diff --git a/board/siemens/dxr2/mux.c b/board/siemens/dxr2/mux.c
index bc80b79..5c22999 100644
--- a/board/siemens/dxr2/mux.c
+++ b/board/siemens/dxr2/mux.c
@@ -63,6 +63,164 @@ static struct module_pin_mux gpios_pin_mux[] = {
{OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)},
{OFFSET(gpmc_csn3), MODE(7) }, /* LED0 GPIO2_0 */
{OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */
+ /* Triacs in HW Rev 2 */
+ {OFFSET(uart1_ctsn), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y5 GPIO0_12*/
+ {OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y3 GPIO2_28*/
+ {OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y7 GPIO2_27*/
+ /* Triacs initial HW Rev */
+ {OFFSET(gpmc_csn1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_30 Y0 */
+ {OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_28 Y1 */
+ {OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_31 Y2 */
+ {OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_11 Y3 */
+ {OFFSET(lcd_data14), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_10 Y4 */
+ {OFFSET(gpmc_clk), MODE(7) | RXACTIVE | PULLUDDIS}, /* 2_1 Y5 */
+ {OFFSET(emu1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 3_8 Y6 */
+ {OFFSET(gpmc_ad15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_15 Y7 */
+ /* Remaining pins that were not used in this file */
+ {OFFSET(gpmc_ad8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_ad9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a10), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_vsync), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_hsync), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_pclk), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_ac_bias_en), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mmc0_dat3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mmc0_dat0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mmc0_clk), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mmc0_cmd), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(spi0_sclk), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(spi0_d0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(spi0_d1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(spi0_cs0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart1_rtsn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart1_rxd), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart1_txd), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_aclkx), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_fsx), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_axr0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_ahclkr), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_aclkr), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_fsr), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_axr1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_ahclkx), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(xdma_event_intr0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(xdma_event_intr1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(nresetin_out), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(porz), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(nnmi), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(osc0_in), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(osc0_out), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(rsvd1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(tms), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(tdi), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(tdo), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(tck), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ntrst), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(osc1_in), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(osc1_out), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(pmic_power_en), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(rtc_porz), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(rsvd2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ext_wakeup), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(enz_kaldo_1p8v), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_dm), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_dp), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_ce), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_id), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_vbus), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_dm), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_dp), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_ce), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_id), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_vbus), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_resetn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_csn0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_cke), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_ck), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_nck), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_casn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_rasn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_wen), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_ba0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_ba1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_ba2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a10), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a11), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a12), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a13), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a14), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a15), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_odt), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d10), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d11), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d12), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d13), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d14), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d15), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqm0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqm1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqs0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqsn0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqs1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqsn1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_vref), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_vtp), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_strben0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_strben1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS},
{-1},
};