summaryrefslogtreecommitdiff
path: root/board/siemens/SCM/fpga_scm.c
diff options
context:
space:
mode:
authorwdenk <wdenk>2004-02-12 00:47:09 +0000
committerwdenk <wdenk>2004-02-12 00:47:09 +0000
commitbf9e3b38f77c2eac620263dd60437c6ec47a27bf (patch)
treed03891090553d167f3eb08d7f9c3f2532e43fcc2 /board/siemens/SCM/fpga_scm.c
parenta2d18bb7d31e7b971386fef505ff0218f3b6e893 (diff)
downloadu-boot-imx-bf9e3b38f77c2eac620263dd60437c6ec47a27bf.zip
u-boot-imx-bf9e3b38f77c2eac620263dd60437c6ec47a27bf.tar.gz
u-boot-imx-bf9e3b38f77c2eac620263dd60437c6ec47a27bf.tar.bz2
* Some code cleanup
* Patch by Josef Baumgartner, 10 Feb 2004: Fixes for Coldfire port * Patch by Brad Kemp, 11 Feb 2004: Fix CFI flash driver problems
Diffstat (limited to 'board/siemens/SCM/fpga_scm.c')
-rw-r--r--board/siemens/SCM/fpga_scm.c134
1 files changed, 67 insertions, 67 deletions
diff --git a/board/siemens/SCM/fpga_scm.c b/board/siemens/SCM/fpga_scm.c
index 3b93794..661bf66 100644
--- a/board/siemens/SCM/fpga_scm.c
+++ b/board/siemens/SCM/fpga_scm.c
@@ -28,77 +28,77 @@
#include "../common/fpga.h"
fpga_t fpga_list[] = {
- { "FIOX" , CFG_FIOX_BASE ,
- CFG_PD_FIOX_INIT , CFG_PD_FIOX_PROG , CFG_PD_FIOX_DONE },
- { "FDOHM", CFG_FDOHM_BASE,
- CFG_PD_FDOHM_INIT, CFG_PD_FDOHM_PROG, CFG_PD_FDOHM_DONE }
+ {"FIOX", CFG_FIOX_BASE,
+ CFG_PD_FIOX_INIT, CFG_PD_FIOX_PROG, CFG_PD_FIOX_DONE}
+ ,
+ {"FDOHM", CFG_FDOHM_BASE,
+ CFG_PD_FDOHM_INIT, CFG_PD_FDOHM_PROG, CFG_PD_FDOHM_DONE}
};
-int fpga_count = sizeof(fpga_list) / sizeof(fpga_t);
+int fpga_count = sizeof (fpga_list) / sizeof (fpga_t);
-ulong fpga_control (fpga_t* fpga, int cmd)
+ulong fpga_control (fpga_t * fpga, int cmd)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+ switch (cmd) {
+ case FPGA_INIT_IS_HIGH:
+ immr->im_ioport.iop_pdird &= ~fpga->init_mask; /* input */
+ return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1 : 0;
+
+ case FPGA_INIT_SET_LOW:
+ immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
+ immr->im_ioport.iop_pdatd &= ~fpga->init_mask;
+ break;
+
+ case FPGA_INIT_SET_HIGH:
+ immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
+ immr->im_ioport.iop_pdatd |= fpga->init_mask;
+ break;
+
+ case FPGA_PROG_SET_LOW:
+ immr->im_ioport.iop_pdatd &= ~fpga->prog_mask;
+ break;
+
+ case FPGA_PROG_SET_HIGH:
+ immr->im_ioport.iop_pdatd |= fpga->prog_mask;
+ break;
+
+ case FPGA_DONE_IS_HIGH:
+ return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1 : 0;
+
+ case FPGA_READ_MODE:
+ break;
+
+ case FPGA_LOAD_MODE:
+ break;
+
+ case FPGA_GET_ID:
+ if (fpga->conf_base == CFG_FIOX_BASE) {
+ ulong ver =
+ *(volatile ulong *) (fpga->conf_base + 0x10);
+ return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0);
+ } else if (fpga->conf_base == CFG_FDOHM_BASE) {
+ return (*(volatile ushort *) fpga->conf_base) & 0xff;
+ } else {
+ return *(volatile ulong *) fpga->conf_base;
+ }
+
+ case FPGA_INIT_PORTS:
+ immr->im_ioport.iop_ppard &= ~fpga->init_mask; /* INIT I/O */
+ immr->im_ioport.iop_psord &= ~fpga->init_mask;
+ immr->im_ioport.iop_pdird &= ~fpga->init_mask;
+
+ immr->im_ioport.iop_ppard &= ~fpga->prog_mask; /* PROG Output */
+ immr->im_ioport.iop_psord &= ~fpga->prog_mask;
+ immr->im_ioport.iop_pdird |= fpga->prog_mask;
+
+ immr->im_ioport.iop_ppard &= ~fpga->done_mask; /* DONE Input */
+ immr->im_ioport.iop_psord &= ~fpga->done_mask;
+ immr->im_ioport.iop_pdird &= ~fpga->done_mask;
+
+ break;
- switch (cmd) {
- case FPGA_INIT_IS_HIGH:
- immr->im_ioport.iop_pdird &= ~fpga->init_mask; /* input */
- return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1:0;
-
- case FPGA_INIT_SET_LOW:
- immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
- immr->im_ioport.iop_pdatd &= ~fpga->init_mask;
- break;
-
- case FPGA_INIT_SET_HIGH:
- immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
- immr->im_ioport.iop_pdatd |= fpga->init_mask;
- break;
-
- case FPGA_PROG_SET_LOW:
- immr->im_ioport.iop_pdatd &= ~fpga->prog_mask;
- break;
-
- case FPGA_PROG_SET_HIGH:
- immr->im_ioport.iop_pdatd |= fpga->prog_mask;
- break;
-
- case FPGA_DONE_IS_HIGH:
- return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1:0;
-
- case FPGA_READ_MODE:
- break;
-
- case FPGA_LOAD_MODE:
- break;
-
- case FPGA_GET_ID:
- if (fpga->conf_base == CFG_FIOX_BASE) {
- ulong ver = *(volatile ulong *)(fpga->conf_base + 0x10);
- return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0);
}
- else if (fpga->conf_base == CFG_FDOHM_BASE) {
- return (*(volatile ushort *)fpga->conf_base) & 0xff;
- }
- else {
- return *(volatile ulong *)fpga->conf_base;
- }
-
- case FPGA_INIT_PORTS:
- immr->im_ioport.iop_ppard &= ~fpga->init_mask; /* INIT I/O */
- immr->im_ioport.iop_psord &= ~fpga->init_mask;
- immr->im_ioport.iop_pdird &= ~fpga->init_mask;
-
- immr->im_ioport.iop_ppard &= ~fpga->prog_mask; /* PROG Output */
- immr->im_ioport.iop_psord &= ~fpga->prog_mask;
- immr->im_ioport.iop_pdird |= fpga->prog_mask;
-
- immr->im_ioport.iop_ppard &= ~fpga->done_mask; /* DONE Input */
- immr->im_ioport.iop_psord &= ~fpga->done_mask;
- immr->im_ioport.iop_pdird &= ~fpga->done_mask;
-
- break;
-
- }
- return 0;
+ return 0;
}