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authorStefan Agner <stefan@agner.ch>2014-03-02 19:46:49 +0100
committerTom Warren <twarren@nvidia.com>2014-04-17 08:41:06 -0700
commitb1d615f3f10294c016cc424ef05e938f49af8117 (patch)
tree09ebc45c451b358b127a37cc02a29469cdb07711 /board/shmin
parentb03f4b3742a728c13a89f3fbf8a9a2ec43061025 (diff)
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usb: tegra: fix PHY configuration
On Tegra30 and later, the PTS (parallel transceiver select) and STS (serial transceiver select) are part of the HOSTPC1_DEVLC_0 register rather than PORTSC1_0 register. Since the reset configuration usually matches the intended configuration, this error did not show up on Tegra30 devices. Also use the slightly different bit fields of first USB, (USBD) on Tegra20 and move those definitions to the Tegra20 specific header file. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tom Warren <twarren@nvidia.com>
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