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authorKumar Gala <galak@kernel.crashing.org>2008-04-29 10:27:08 -0500
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-04-29 11:44:29 -0500
commit45239cf4152109caa925145ccd433529902df887 (patch)
treecbeedce4c8e289bf2da8f6a4afa3677f57578ccd /board/sbc8641d
parentef7d30b14394e4c4a153118f5845760cadada02a (diff)
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85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docs
All the 85xx and 86xx UM describe the register as timing_cfg_3 not as ext_refrec. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/sbc8641d')
-rw-r--r--board/sbc8641d/sbc8641d.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index b3dd9c8..519f332 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -135,7 +135,7 @@ long int fixed_sdram (void)
ddr->cs1_config = CFG_DDR_CS1_CONFIG;
ddr->cs2_config = CFG_DDR_CS2_CONFIG;
ddr->cs3_config = CFG_DDR_CS3_CONFIG;
- ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
+ ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
@@ -166,7 +166,7 @@ long int fixed_sdram (void)
ddr->cs1_config = CFG_DDR2_CS1_CONFIG;
ddr->cs2_config = CFG_DDR2_CS2_CONFIG;
ddr->cs3_config = CFG_DDR2_CS3_CONFIG;
- ddr->ext_refrec = CFG_DDR2_EXT_REFRESH;
+ ddr->timing_cfg_3 = CFG_DDR2_EXT_REFRESH;
ddr->timing_cfg_0 = CFG_DDR2_TIMING_0;
ddr->timing_cfg_1 = CFG_DDR2_TIMING_1;
ddr->timing_cfg_2 = CFG_DDR2_TIMING_2;