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| author | Peter Tyser <ptyser@xes-inc.com> | 2009-07-17 10:14:45 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-07-22 09:43:47 -0500 |
| commit | e7ee23ec1788d8cf269a4cf6b9cd3722cbc7d592 (patch) | |
| tree | d849696bd6a8c4f4f561381bbec53b5c82f5dacf /board/sbc8641d/sbc8641d.c | |
| parent | f6155c6fbb1d85f517b7c160570f0995ef14c43f (diff) | |
| download | u-boot-imx-e7ee23ec1788d8cf269a4cf6b9cd3722cbc7d592.zip u-boot-imx-e7ee23ec1788d8cf269a4cf6b9cd3722cbc7d592.tar.gz u-boot-imx-e7ee23ec1788d8cf269a4cf6b9cd3722cbc7d592.tar.bz2 | |
86xx: Rename ccsr_ddr's sdram_mode_1, sdram_cfg_1 fields
Rename sdram_mode_1 to sdram_mode and sdram_cfg_1 to sdram_cfg to match
the 86xx user's manual and other Freescale architectures
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/sbc8641d/sbc8641d.c')
| -rw-r--r-- | board/sbc8641d/sbc8641d.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index c39d2c0..f118a6e 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -127,9 +127,9 @@ long int fixed_sdram (void) ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1A; + ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A; ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2; - ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL; ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; @@ -140,7 +140,7 @@ long int fixed_sdram (void) udelay (500); - ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1B; + ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B; asm ("sync; isync"); udelay (500); @@ -158,9 +158,9 @@ long int fixed_sdram (void) ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0; ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1; ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2; - ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1A; + ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A; ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2; - ddr->sdram_mode_1 = CONFIG_SYS_DDR2_MODE_1; + ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1; ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2; ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL; ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL; @@ -171,7 +171,7 @@ long int fixed_sdram (void) udelay (500); - ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1B; + ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B; asm ("sync; isync"); udelay (500); |