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| author | Kumar Gala <galak@kernel.crashing.org> | 2007-12-19 01:18:15 -0600 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-01-09 16:25:03 -0600 |
| commit | 2146cf56821c3364786ca94a7306008c5824b238 (patch) | |
| tree | 428acd2d62caa2aad074a5ac37c33817835cfb8a /board/sbc8560 | |
| parent | 1d47273d46925929f8f2c1913cd96d7257aade88 (diff) | |
| download | u-boot-imx-2146cf56821c3364786ca94a7306008c5824b238.zip u-boot-imx-2146cf56821c3364786ca94a7306008c5824b238.tar.gz u-boot-imx-2146cf56821c3364786ca94a7306008c5824b238.tar.bz2 | |
Reworked FSL Book-E TLB macros to be more readable
The old macros made it difficult to know what WIMGE and perm bits
were set for a TLB entry. Actually use the bit masks for these items
since they are only a single bit.
Also moved the macros into mmu.h out of e500.h since they aren't specific
to e500.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/sbc8560')
| -rw-r--r-- | board/sbc8560/init.S | 94 |
1 files changed, 47 insertions, 47 deletions
diff --git a/board/sbc8560/init.S b/board/sbc8560/init.S index 3d8d180..95cb85a 100644 --- a/board/sbc8560/init.S +++ b/board/sbc8560/init.S @@ -97,69 +97,69 @@ tlb1_entry: /* TLB for CCSRBAR (IMMR) */ - .long TLB1_MAS0(1,1,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1,1,0) + .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) + .long FSL_BOOKE_MAS2(CFG_CCSRBAR,(MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_CCSRBAR,0,(MAS3_SX|MAS3_SW|MAS3_SR)) /* TLB for Local Bus stuff, just map the whole 512M */ /* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */ - .long TLB1_MAS0(1,2,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long TLB1_MAS2(((0xe0000000>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((0xe0000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1,2,0) + .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long FSL_BOOKE_MAS2(0xe0000000,(MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(0xe0000000,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - .long TLB1_MAS0(1,3,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long TLB1_MAS2(((0xf0000000>>12)&0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((0xf0000000>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1,3,0) + .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long FSL_BOOKE_MAS2(0xf0000000,(MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(0xf0000000,0,(MAS3_SX|MAS3_SW|MAS3_SR)) #if !defined(CONFIG_SPD_EEPROM) - .long TLB1_MAS0(1,4,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0) - .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,5,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0) - .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1,4,0) + .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE,0) + .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) + + .long FSL_BOOKE_MAS0(1,5,0) + .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x10000000,0) + .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x10000000,0,(MAS3_SX|MAS3_SW|MAS3_SR)) #else - .long TLB1_MAS0(1,4,0) - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,5,0) - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1,4,0) + .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long FSL_BOOKE_MAS2(0,0) + .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) + + .long FSL_BOOKE_MAS0(1,5,0) + .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long FSL_BOOKE_MAS2(0,0) + .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) #endif - .long TLB1_MAS0(1,6,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) + .long FSL_BOOKE_MAS0(1,6,0) + .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) #ifdef CONFIG_L2_INIT_RAM - .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0) + .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0,0,0,1,0,0,0,0) #else - .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0) + .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0) #endif - .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - .long TLB1_MAS0(1,7,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1,7,0) + .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long FSL_BOOKE_MAS2(CFG_PCI_MEM_BASE,(MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI_MEM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - .long TLB1_MAS0(1,15,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1,15,0) + .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) + .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT,(MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT,0,(MAS3_SX|MAS3_SW|MAS3_SR)) #else - .long TLB1_MAS0(1,15,0) - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1,15,0) + .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long FSL_BOOKE_MAS2(0,0) + .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) #endif entry_end |