sbc8548: relocate 64MB user flash to sane boundary

The current situation has the 64MB user flash at an awkward
alignment; shifted back from 0xfc00_0000 by 8M, to leave an 8MB hole
for the soldered on boot flash @ EOM.  But to switch to optionally
supporting booting off the 64MB flash, the 64MB will then be mapped
at the sane address of 0xfc00_0000.

This leads to awkward things when programming the 64MB flash prior
to transitioning to it -- i.e. even though the chip spans from
0xfb80_0000 to 0xff7f_ffff, you would have to program a u-boot image
into the two sectors from 0xfbf0_0000 --> 0xfbff_ffff so that it was
in the right place when JP12/SW2.8 were switched to make the 64MB on
/CS0. (i.e. the chip is only looking at the bits in mask 0x3ff_ffff)

We also have to have three TLB entries responsible for dealing with
mapping the 64MB flash due to this 8MB of misalignment.

In the end, there is address space from 0xec00_0000 to 0xefff_ffff
where we can map it, and then the transition from booting from one
config to the other will be a simple 0xec --> 0xfc mapping.  Plus we
can toss out a TLB entry.

Note that TLB0 is kept at 64MB and not shrunk down to the 8MB boot
flash; this means we won't have to change it when the alternate
config uses the full 64MB for booting, in TLB0.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

2 files changed, 10 insertions, 16 deletions

diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index 5fa9db0..febb682 100644
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -36,9 +36,9 @@
  * 0xe000_0000	0xe000_ffff	CCSR			1M
  * 0xe200_0000	0xe27f_ffff	PCI1 IO			8M
  * 0xe280_0000	0xe2ff_ffff	PCIe IO			8M
+ * 0xec00_0000	0xefff_ffff	FLASH (2nd bank)	64M
  * 0xf000_0000	0xf7ff_ffff	SDRAM			128M
  * 0xf8b0_0000	0xf80f_ffff	EEPROM			1M
- * 0xfb80_0000	0xff7f_ffff	FLASH (2nd bank)	64M
  * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M
  *
  * Notes:
@@ -47,6 +47,7 @@
  */
 
 struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
 #ifndef CONFIG_SPD_EEPROM
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
 #endif
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index bb4c052..e9cedc7 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -46,12 +46,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 	/*
 	 * TLB 0:	64M	Non-cacheable, guarded
-	 * 0xfc000000	56M	8MB -> 64MB of user flash
+	 * 0xfc000000	56M	unused
 	 * 0xff800000	8M	boot FLASH
+	 *	.... or ....
+	 * 0xfc000000	64M	user flash
+	 *
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x800000,
-		      CONFIG_SYS_ALT_FLASH + 0x800000,
+	SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_64M, 1),
 
@@ -103,21 +105,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      0, 5, BOOKE_PAGESZ_16M, 1),
 
 	/*
-	 * TLB 6:	4M	Non-cacheable, guarded
-	 * 0xfb800000	4M	1st 4MB block of 64MB user FLASH
+	 * TLB 6:	64M	Non-cacheable, guarded
+	 * 0xec000000	64M	64MB user FLASH
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_4M, 1),
-
-	/*
-	 * TLB 7:	4M	Non-cacheable, guarded
-	 * 0xfbc00000	4M	2nd 4MB block of 64MB user FLASH
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
-		      CONFIG_SYS_ALT_FLASH + 0x400000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_4M, 1),
+		      0, 6, BOOKE_PAGESZ_64M, 1),
 
 };