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| author | Paul Gortmaker <paul.gortmaker@windriver.com> | 2009-09-23 17:30:57 -0400 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-09-24 12:04:59 -0500 |
| commit | ded58f4153923dfff16d2f96495bd7acf1f7e10e (patch) | |
| tree | b0a4eb2382c12f7622a3ac321dd381b508cf9004 /board/sbc8548/tlb.c | |
| parent | 2c40acd3525b75db3fcd3f5a5bd40445679b5547 (diff) | |
| download | u-boot-imx-ded58f4153923dfff16d2f96495bd7acf1f7e10e.zip u-boot-imx-ded58f4153923dfff16d2f96495bd7acf1f7e10e.tar.gz u-boot-imx-ded58f4153923dfff16d2f96495bd7acf1f7e10e.tar.bz2 | |
sbc8548: cosmetic line re-wrap
Fix the extra long lines to be consistent with u-boot coding style.
No functional change here.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Diffstat (limited to 'board/sbc8548/tlb.c')
| -rw-r--r-- | board/sbc8548/tlb.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 18d11f6..ddcb532 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -31,13 +31,16 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -62,7 +65,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), |