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| author | Paul Gortmaker <paul.gortmaker@windriver.com> | 2011-12-30 23:53:10 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2012-01-11 13:59:07 -0600 |
| commit | 7e44f2b710db09a1b02e55246e0915732cc4775e (patch) | |
| tree | e94b2b4fa41c941841bcb5b61214e3b9b82f12d3 /board/sbc8548/tlb.c | |
| parent | 5f4c6f0db930646e9ca3b479b5fe9b8d2691fa77 (diff) | |
| download | u-boot-imx-7e44f2b710db09a1b02e55246e0915732cc4775e.zip u-boot-imx-7e44f2b710db09a1b02e55246e0915732cc4775e.tar.gz u-boot-imx-7e44f2b710db09a1b02e55246e0915732cc4775e.tar.bz2 | |
sbc8548: Make enabling SPD RAM configuration work
Previously, SPD configuration of RAM was non functional on
this board. Now that the root cause is known (an i2c address
conflict), there is a simple end-user workaround - remove the
old slower local bus 128MB module and then SPD detection on the
main DDR2 memory module works fine.
We make the enablement of the LBC SDRAM support conditional on
being not SPD enabled. We can revisit this dependency as the
hardware workaround becomes available.
Turning off LBC SDRAM support revealed a couple implict dependencies
in the tlb/law code that always expected an LBC SDRAM address.
This has been tested with the default 256MB module, a 512MB
a 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration
worked fine in all cases.
The default configuration remains to go with the hard coded
DDR config, so the default build will continue to work on boards
where people don't bother to read the docs. But the advantage
of going to the SPD config is that even the small default module
gets configured for CL3 instead of CL4.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/sbc8548/tlb.c')
| -rw-r--r-- | board/sbc8548/tlb.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 4bf7214..af927f1 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -76,6 +76,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_64M, 1), +#ifdef CONFIG_SYS_LBC_SDRAM_BASE /* * TLB 3: 64M Cacheable, non-guarded * 0xf0000000 64M LBC SDRAM First half @@ -92,6 +93,7 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 4, BOOKE_PAGESZ_64M, 1), +#endif /* * TLB 5: 16M Cacheable, non-guarded |