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| author | Poonam Aggrwal <poonam.aggrwal@freescale.com> | 2009-09-19 17:50:17 +0530 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-09-24 12:04:59 -0500 |
| commit | 82b7725b6d46d9ad2b962b4cdfa896bd5ee32fb5 (patch) | |
| tree | f3b4cf35403ab7d75034567e52011b1d57fbb56a /board/sbc8548/sbc8548.c | |
| parent | bd42bbb858dde713f023fc2e4f512ec174a1a8d2 (diff) | |
| download | u-boot-imx-82b7725b6d46d9ad2b962b4cdfa896bd5ee32fb5.zip u-boot-imx-82b7725b6d46d9ad2b962b4cdfa896bd5ee32fb5.tar.gz u-boot-imx-82b7725b6d46d9ad2b962b4cdfa896bd5ee32fb5.tar.bz2 | |
ppc/85xx: 32bit DDR changes for P1020/P1011
The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010
where max DDR data width supported is 64bit.
As a next step the DDR data width initialization would be made more dynamic
with more flexibility from the board perspective and user choice.
Going forward we would also remove the hardcodings for platforms with onboard
memories and try to use the FSL SPD code for DDR initialization.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/sbc8548/sbc8548.c')
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