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authorPaul Gortmaker <paul.gortmaker@windriver.com>2009-09-20 20:36:04 -0400
committerKumar Gala <galak@kernel.crashing.org>2009-09-24 12:05:00 -0500
commit11d5a629f8a40f9d7cffc74e58f4e3ed258e56ab (patch)
tree084dfd5667b06957a383a14c5a67bdbaf4b10ad6 /board/sbc8548/sbc8548.c
parent0c7e4d45d9fb3c9e503ee93d50572d346dae150e (diff)
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sbc8548: correct local bus SDRAM size from 64M to 128M
The size of the LB SDRAM on this board is 128MB, spanning CS3 and CS4. It was previously only being configured for 64MB on CS3, since that was what the original codebase of the MPC8548CDS had. In addition to setting up BR4/OR4, this also adds the TLB entry for the second half of the SDRAM. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/sbc8548/sbc8548.c')
-rw-r--r--board/sbc8548/sbc8548.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index ce998e1..f4bfd92 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -149,7 +149,7 @@ local_bus_init(void)
void
sdram_init(void)
{
-#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
+#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
uint idx;
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
@@ -169,6 +169,12 @@ sdram_init(void)
out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
asm("msync");
+ out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM);
+ asm("msync");
+
+ out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM);
+ asm("msync");
+
out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
asm("msync");