Add Sandburst Metrobox and Sandburst Karef board support packages.

Second serial port on 440GX now defined as a system device.
Add 'Short Etch' code for Cicada PHY within 440gx_enet.c
Patch by Travis B. Sawyer, 12 Jul 2005

Check return value of malloc in 440gx_enet.c
Patch by Travis B. Sawyer, 18 Jul 2005

10 files changed, 2373 insertions, 0 deletions

diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile
new file mode 100644
index 0000000..8b3173c
--- /dev/null
+++ b/board/sandburst/karef/Makefile
@@ -0,0 +1,59 @@
+#
+# (C) Copyright 2005
+# Sandburst Corporation
+# Travis B. Sawyer
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# TBS: add for debugging purposes
+BUILDUSER := $(shell whoami)
+FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o)
+
+CFLAGS += -DBUILDUSER='"$(BUILDUSER)"'
+# TBS: end debugging
+
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
+	../common/sb_common.o
+
+SOBJS	= init.o
+
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/sandburst/karef/config.mk b/board/sandburst/karef/config.mk
new file mode 100644
index 0000000..65c1e48
--- /dev/null
+++ b/board/sandburst/karef/config.mk
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2005
+# Sandburst Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Sandburst Corporation Metrobox Reference Design
+# Travis B. Sawyer
+#
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/sandburst/karef/hal_ka_of_auto.h b/board/sandburst/karef/hal_ka_of_auto.h
new file mode 100644
index 0000000..cc501c9
--- /dev/null
+++ b/board/sandburst/karef/hal_ka_of_auto.h
@@ -0,0 +1,324 @@
+/* ****************************************************************
+ * Common defs for reg spec for chip ka_of
+ * Auto-generated by trex2: DO NOT HAND-EDIT!!
+ * ****************************************************************
+ */
+
+#ifndef HAL_KA_OF_AUTO_H
+#define HAL_KA_OF_AUTO_H
+
+
+/* ----------------------------------------------------------------
+ * For block: 'ofem'
+ */
+
+/* ---- Block instance addressing (for block-select) */
+#define OFEM_BLOCK_ADDR_BIT_L 6
+#define OFEM_BLOCK_ADDR_BIT_H 9
+#define OFEM_BLOCK_ADDR_WIDTH 4
+
+#define  OFEM_ADDR  0x0
+
+/* ---- Reg addressing (within block) */
+#define OFEM_REG_ADDR_BIT_L 2
+#define OFEM_REG_ADDR_BIT_H 5
+#define OFEM_REG_ADDR_WIDTH 4
+
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_REVISION */
+#define SAND_HAL_KA_OF_OFEM_REVISION_OFFSET    0x000
+#ifndef SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_REVISION_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_REVISION_MSB     31
+#define SAND_HAL_KA_OF_OFEM_REVISION_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_RESET */
+#define SAND_HAL_KA_OF_OFEM_RESET_OFFSET    0x004
+#ifndef SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_RESET_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_RESET_MSB     31
+#define SAND_HAL_KA_OF_OFEM_RESET_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_CNTL */
+#define SAND_HAL_KA_OF_OFEM_CNTL_OFFSET    0x018
+#ifndef SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_CNTL_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_CNTL_MSB     31
+#define SAND_HAL_KA_OF_OFEM_CNTL_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_MAC_FLOW_CTL */
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_OFFSET    0x01c
+#ifndef SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MSB     31
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_INTERRUPT */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_OFFSET    0x008
+#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MSB     31
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_INTERRUPT_MASK */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_OFFSET    0x00c
+#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MSB     31
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_SCRATCH */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_OFFSET    0x010
+#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MSB     31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_SCRATCH_MASK */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_OFFSET    0x014
+#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MSB     31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_LSB      0
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_REVISION */
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK    0x0000ff00
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT    8
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MSB    15
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_LSB    8
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_DEFAULT    0x00000024
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK    0x000000ff
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MSB    7
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_LSB    0
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_RESET */
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK    0x00000004
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_SHIFT    2
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MSB    2
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_LSB    2
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK    0x00000002
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_SHIFT    1
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MSB    1
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_LSB    1
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK    0x00000001
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MSB    0
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_LSB    0
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_CNTL */
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MASK    0x000000c0
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_SHIFT    6
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MSB    7
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_LSB    6
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK    0x00000030
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT    4
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MSB    5
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_LSB    4
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MASK    0x0000000c
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_SHIFT    2
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MSB    3
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_LSB    2
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MASK    0x00000003
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MSB    1
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_LSB    0
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_MAC_FLOW_CTL */
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MASK    0x00000100
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_SHIFT    8
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MSB    8
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_LSB    8
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK    0x00000010
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT    4
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB    4
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB    4
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK    0x0000000f
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB    3
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB    0
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_INTERRUPT */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MASK    0x00000100
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_SHIFT    8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MSB    8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_LSB    8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MASK    0x00000080
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_SHIFT    7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MSB    7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_LSB    7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MASK    0x00000040
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_SHIFT    6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MSB    6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_LSB    6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MASK    0x00000020
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_SHIFT    5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MSB    5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_LSB    5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MASK    0x00000010
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_SHIFT    4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MSB    4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_LSB    4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MASK    0x00000008
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_SHIFT    3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MSB    3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_LSB    3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MASK    0x00000004
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_SHIFT    2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MSB    2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_LSB    2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MASK    0x00000002
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_SHIFT    1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MSB    1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_LSB    1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MASK    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MSB    0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_LSB    0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_INTERRUPT_MASK */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK    0x00000100
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT    8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB    8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB    8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK    0x00000080
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT    7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB    7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB    7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK    0x00000040
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT    6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB    6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB    6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK    0x00000020
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT    5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB    5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB    5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK    0x00000010
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT    4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB    4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB    4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK    0x00000008
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT    3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB    3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB    3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK    0x00000004
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT    2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB    2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB    2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK    0x00000002
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT    1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB    1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB    1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB    0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB    0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT    0x00000001
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_SCRATCH */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MSB    31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_LSB    0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_SCRATCH_MASK */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MSB    31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_LSB    0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT    0xffffffff
+
+#endif /* matches #ifndef HAL_KA_OF_AUTO_H */
diff --git a/board/sandburst/karef/hal_ka_sc_auto.h b/board/sandburst/karef/hal_ka_sc_auto.h
new file mode 100644
index 0000000..db1cec2
--- /dev/null
+++ b/board/sandburst/karef/hal_ka_sc_auto.h
@@ -0,0 +1,836 @@
+/* ****************************************************************
+ * Common defs for reg spec for chip ka_sc
+ * Auto-generated by trex2: DO NOT HAND-EDIT!!
+ * ****************************************************************
+ */
+
+#ifndef HAL_KA_SC_AUTO_H
+#define HAL_KA_SC_AUTO_H
+
+
+/* ----------------------------------------------------------------
+ * For block: 'scan'
+ */
+
+/* ---- Block instance addressing (for block-select) */
+#define SCAN_BLOCK_ADDR_BIT_L 7
+#define SCAN_BLOCK_ADDR_BIT_H 9
+#define SCAN_BLOCK_ADDR_WIDTH 3
+
+#define  SCAN_ADDR  0x0
+
+/* ---- Reg addressing (within block) */
+#define SCAN_REG_ADDR_BIT_L 2
+#define SCAN_REG_ADDR_BIT_H 6
+#define SCAN_REG_ADDR_WIDTH 5
+
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_REVISION */
+#define SAND_HAL_KA_SC_SCAN_REVISION_OFFSET    0x000
+#ifndef SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_REVISION_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_REVISION_MSB     31
+#define SAND_HAL_KA_SC_SCAN_REVISION_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_RESET */
+#define SAND_HAL_KA_SC_SCAN_RESET_OFFSET    0x004
+#ifndef SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_RESET_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_RESET_MSB     31
+#define SAND_HAL_KA_SC_SCAN_RESET_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_STATUS */
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFFSET    0x008
+#ifndef SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_STATUS_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_STATUS_MSB     31
+#define SAND_HAL_KA_SC_SCAN_STATUS_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_CNTL */
+#define SAND_HAL_KA_SC_SCAN_CNTL_OFFSET    0x01c
+#ifndef SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_CNTL_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_CNTL_MSB     31
+#define SAND_HAL_KA_SC_SCAN_CNTL_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_INFO */
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_OFFSET    0x020
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MSB     31
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_FROM_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_OFFSET    0x024
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_FROM_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_OFFSET    0x028
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_TO_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_OFFSET    0x02c
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_TO_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_OFFSET    0x030
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_CTRL */
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_OFFSET    0x034
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_PLL_CTRL */
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_OFFSET    0x038
+#ifndef SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MSB     31
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_CORE_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_OFFSET    0x03c
+#ifndef SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MSB     31
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_DR_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_OFFSET    0x040
+#ifndef SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MSB     31
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SPI_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_OFFSET    0x044
+#ifndef SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_BRD_OUT_DATA */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_OFFSET    0x048
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MSB     31
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_OFFSET    0x04c
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MSB     31
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_BRD_IN */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_OFFSET    0x050
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MSB     31
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_MISC */
+#define SAND_HAL_KA_SC_SCAN_MISC_OFFSET    0x054
+#ifndef SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_MISC_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_MISC_MSB     31
+#define SAND_HAL_KA_SC_SCAN_MISC_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_INTERRUPT */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OFFSET    0x00c
+#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MSB     31
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_INTERRUPT_MASK */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OFFSET    0x010
+#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MSB     31
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCRATCH */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_OFFSET    0x014
+#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCRATCH_MASK */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_OFFSET    0x018
+#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_LSB      0
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_REVISION */
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK    0x0000ff00
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT    8
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MSB    15
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_LSB    8
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_DEFAULT    0x00000023
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK    0x000000ff
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MSB    7
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_LSB    0
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_RESET */
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK    0x00000200
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_SHIFT    9
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MSB    9
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_LSB    9
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK    0x00000100
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_SHIFT    8
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MSB    8
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_LSB    8
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK    0x00000080
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_SHIFT    7
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MSB    7
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_LSB    7
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK    0x00000040
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_SHIFT    6
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MSB    6
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_LSB    6
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK    0x00000020
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_SHIFT    5
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MSB    5
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_LSB    5
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK    0x00000010
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MSB    4
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_LSB    4
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK    0x00000008
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_SHIFT    3
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MSB    3
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_LSB    3
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK    0x00000002
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_SHIFT    1
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MSB    1
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_LSB    1
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK    0x00000001
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MSB    0
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_LSB    0
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_STATUS */
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MASK    0x00000040
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_SHIFT    6
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MSB    6
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_LSB    6
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MASK    0x00000020
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_SHIFT    5
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MSB    5
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_LSB    5
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MASK    0x00000010
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MSB    4
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_LSB    4
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MASK    0x00000008
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_SHIFT    3
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MSB    3
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_LSB    3
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MASK    0x00000004
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_SHIFT    2
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MSB    2
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_LSB    2
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MASK    0x00000002
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_SHIFT    1
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MSB    1
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_LSB    1
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MASK    0x00000001
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MSB    0
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_LSB    0
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_CNTL */
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MASK    0x00000400
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_SHIFT    10
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MSB    10
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_LSB    10
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MASK    0x00000200
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_SHIFT    9
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MSB    9
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_LSB    9
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_DEFAULT    0x00000001
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MASK    0x00000100
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_SHIFT    8
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MSB    8
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_LSB    8
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_DEFAULT    0x00000001
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MASK    0x000000c0
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_SHIFT    6
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MSB    7
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_LSB    6
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK    0x00000030
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MSB    5
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_LSB    4
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MASK    0x0000000c
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_SHIFT    2
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MSB    3
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_LSB    2
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MASK    0x00000003
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MSB    1
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_LSB    0
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_INFO */
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK    0x0000f000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT    12
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MSB    15
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_LSB    12
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK    0x00000300
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT    8
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MSB    9
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_LSB    8
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK    0x000000f0
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MSB    7
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_LSB    4
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK    0x00000003
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MSB    1
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_LSB    0
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_FROM_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MSB    31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_FROM_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MSB    31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_TO_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MSB    31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_TO_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MSB    31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_CTRL */
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MASK    0x04000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_SHIFT    26
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MSB    26
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_LSB    26
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MASK    0x03000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_SHIFT    24
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MSB    25
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_LSB    24
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MASK    0x00100000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_SHIFT    20
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MSB    20
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_LSB    20
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MASK    0x00080000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_SHIFT    19
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MSB    19
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_LSB    19
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MASK    0x00040000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_SHIFT    18
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MSB    18
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_LSB    18
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MASK    0x00020000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_SHIFT    17
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MSB    17
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_LSB    17
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MASK    0x00010000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_SHIFT    16
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MSB    16
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_LSB    16
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MASK    0x00001000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_SHIFT    12
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MSB    12
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_LSB    12
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MASK    0x00000800
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SHIFT    11
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MSB    11
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_LSB    11
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MASK    0x00000400
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SHIFT    10
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MSB    10
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_LSB    10
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MASK    0x00000200
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SHIFT    9
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MSB    9
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_LSB    9
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MASK    0x00000100
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SHIFT    8
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MSB    8
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_LSB    8
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MASK    0x00000018
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_SHIFT    3
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MSB    4
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_LSB    3
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MASK    0x00000004
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_SHIFT    2
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MSB    2
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_LSB    2
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MASK    0x00000002
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_SHIFT    1
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MSB    1
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_LSB    1
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MASK    0x00000001
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MSB    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_PLL_CTRL */
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MASK    0x00002000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_SHIFT    13
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MSB    13
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_LSB    13
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MASK    0x00001000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_SHIFT    12
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MSB    12
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_LSB    12
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MASK    0x00000800
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_SHIFT    11
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MSB    11
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_LSB    11
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MASK    0x00000400
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_SHIFT    10
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MSB    10
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_LSB    10
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MASK    0x00000200
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_SHIFT    9
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MSB    9
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_LSB    9
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MASK    0x00000100
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_SHIFT    8
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MSB    8
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_LSB    8
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MASK    0x00000080
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_SHIFT    7
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MSB    7
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_LSB    7
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MASK    0x00000040
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_SHIFT    6
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MSB    6
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_LSB    6
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MASK    0x00000020
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_SHIFT    5
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MSB    5
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_LSB    5
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MASK    0x00000010
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MSB    4
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_LSB    4
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MASK    0x00000008
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_SHIFT    3
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MSB    3
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_LSB    3
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MASK    0x00000007
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MSB    2
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_LSB    0
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_CORE_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK    0x02000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT    25
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB    25
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB    25
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK    0x01000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT    24
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB    24
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB    24
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MASK    0x00ffffff
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MSB    23
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_DR_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK    0x02000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT    25
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB    25
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB    25
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK    0x01000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT    24
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB    24
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB    24
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MASK    0x00ffffff
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MSB    23
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SPI_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK    0x02000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT    25
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB    25
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB    25
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK    0x01000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT    24
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB    24
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB    24
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MASK    0x00ffffff
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MSB    23
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_BRD_OUT_DATA */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MASK    0x001fffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MSB    20
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MASK    0x001fffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MSB    20
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_LSB    0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_BRD_IN */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MASK    0x001fffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MSB    20
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_LSB    0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_MISC */
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MASK    0x00000002
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_SHIFT    1
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MSB    1
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_LSB    1
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MASK    0x00000001
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MSB    0
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_LSB    0
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_INTERRUPT */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MASK    0x00000010
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MSB    4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_LSB    4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MASK    0x00000008
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_SHIFT    3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MSB    3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_LSB    3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MASK    0x00000004
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_SHIFT    2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MSB    2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_LSB    2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MASK    0x00000002
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_SHIFT    1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MSB    1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_LSB    1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MASK    0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MSB    0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_LSB    0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_INTERRUPT_MASK */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK    0x00000010
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB    4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB    4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK    0x00000008
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT    3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB    3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB    3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK    0x00000004
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT    2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB    2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB    2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK    0x00000002
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT    1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB    1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB    1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK    0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB    0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT    0x00000001
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCRATCH */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MSB    31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCRATCH_MASK */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MSB    31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT    0xffffffff
+
+#endif /* matches #ifndef HAL_KA_SC_AUTO_H */
diff --git a/board/sandburst/karef/init.S b/board/sandburst/karef/init.S
new file mode 100644
index 0000000..b1d47a4
--- /dev/null
+++ b/board/sandburst/karef/init.S
@@ -0,0 +1,101 @@
+/*
+*  Copyright (C) 2005 Sandburst Corporation
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+/*
+ * Ported from Ebony init.S by Travis B. Sawyer
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbtab_end
diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c
new file mode 100644
index 0000000..7a98f5b
--- /dev/null
+++ b/board/sandburst/karef/karef.c
@@ -0,0 +1,607 @@
+/*
+ *  Copyright (C) 2005 Sandburst Corporation
+ *  Travis B. Sawyer
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include "karef.h"
+#include "karef_version.h"
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include "../common/sb_common.h"
+#include "../common/ppc440gx_i2c.h"
+
+
+
+void fpga_init (void);
+
+KAREF_BOARD_ID_ST board_id_as[] =
+{
+	{"Undefined"},			     /* Not specified */
+	{"Kamino Reference Design"},
+	{"Reserved"},			     /* Reserved for future use */
+	{"Reserved"},			     /* Reserved for future use */
+};
+
+KAREF_BOARD_ID_ST ofem_board_id_as[] =
+{
+	{"Undefined"},
+	{"1x10 + 10x2"},
+	{"Reserved"},
+	{"Reserved"},
+};
+
+
+/*************************************************************************
+ *  board_early_init_f
+ *
+ *  Setup chip selects, initialize the Opto-FPGA, initialize
+ *  interrupt polarity and triggers.
+ *
+ ************************************************************************/
+int board_early_init_f (void)
+{
+	ppc440_gpio_regs_t *gpio_regs;
+
+	/* Enable GPIO interrupts */
+	mtsdr(sdr_pfc0, 0x00103E00);
+
+	/* Setup access for LEDs, and system topology info */
+	gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+	gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
+	gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
+
+	/* Turn on all the leds for now */
+	gpio_regs->out = SBCOMMON_GPIO_LEDS;
+
+	/*--------------------------------------------------------------------+
+	  | Initialize EBC CONFIG
+	  +-------------------------------------------------------------------*/
+	mtebc(xbcfg,
+	      EBC_CFG_LE_UNLOCK	   | EBC_CFG_PTD_ENABLE |
+	      EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
+	      EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
+	      EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
+	      EBC_CFG_PR_32);
+
+	/*--------------------------------------------------------------------+
+	  | 1/2 MB FLASH. Initialize bank 0 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(pb0ap,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+	/*--------------------------------------------------------------------+
+	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(pb1ap,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+
+	/*--------------------------------------------------------------------+
+	  | Compact Flash, uses 2 Chip Selects (2 & 6)
+	  +-------------------------------------------------------------------*/
+	mtebc(pb2ap,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+	/*--------------------------------------------------------------------+
+	  | KaRef Scan FPGA. Initialize bank 3 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(pb5ap,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+	mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*--------------------------------------------------------------------+
+	  | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
+	  | Initialize bank 4 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(pb4ap,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+	mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
+	      EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*--------------------------------------------------------------------+
+	  | OFEM FPGA  Initialize bank 5 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(pb3ap,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+
+	mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+
+	/*--------------------------------------------------------------------+
+	  | Compact Flash, uses 2 Chip Selects (2 & 6)
+	  +-------------------------------------------------------------------*/
+	mtebc(pb6ap,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+	/*--------------------------------------------------------------------+
+	  | BME-32. Initialize bank 7 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(pb7ap,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+	mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+
+	/*--------------------------------------------------------------------+
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 +-------------------------------------------------------------------*/
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+	mtdcr (uic0er, 0x00000000);	/* disable all */
+	mtdcr (uic0cr, 0x00000000);	/* all non- critical */
+	mtdcr (uic0pr, 0xfffffe03);	/* polarity */
+	mtdcr (uic0tr, 0x01c00000);	/* trigger edge vs level */
+	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+	mtdcr (uic1er, 0x00000000);	/* disable all */
+	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic1pr, 0xffffc8ff);	/* polarity */
+	mtdcr (uic1tr, 0x00ff0000);	/* trigger edge vs level */
+	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+	mtdcr (uic2er, 0x00000000);	/* disable all */
+	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic2pr, 0xffff83ff);	/* polarity */
+	mtdcr (uic2tr, 0x00ff8c0f);	/* trigger edge vs level */
+	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uicb0sr, 0xfc000000);	/* clear all */
+	mtdcr (uicb0er, 0x00000000);	/* disable all */
+	mtdcr (uicb0cr, 0x00000000);	/* all non-critical */
+	mtdcr (uicb0pr, 0xfc000000);
+	mtdcr (uicb0tr, 0x00000000);
+	mtdcr (uicb0vr, 0x00000001);
+
+	fpga_init();
+
+	return 0;
+}
+
+
+/*************************************************************************
+ *  checkboard
+ *
+ *  Dump pertinent info to the console
+ *
+ ************************************************************************/
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+	unsigned char brd_rev, brd_id;
+	unsigned short sernum;
+	unsigned char scan_rev, scan_id, ofem_rev, ofem_id;
+	unsigned char ofem_brd_rev, ofem_brd_id;
+	KAREF_FPGA_REGS_ST *karef_ps;
+	OFEM_FPGA_REGS_ST *ofem_ps;
+
+	karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+	ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
+
+	scan_id = (unsigned char)((karef_ps->revision_ul &
+				   SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
+				  >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
+
+	scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
+				   >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
+
+	brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
+				  >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
+
+	brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
+				 >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
+
+	ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
+				      >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
+
+	ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
+				       >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
+
+	if (0xF != ofem_brd_id) {
+		ofem_id = (unsigned char)((ofem_ps->revision_ul &
+					   SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
+					  >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
+
+		ofem_rev = (unsigned char)((ofem_ps->revision_ul &
+					    SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
+					   >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
+	}
+
+	get_sys_info (&sysinfo);
+
+	sernum = sbcommon_get_serial_number();
+
+	printf ("Board: Sandburst Corporation Kamino Reference Design "
+		"Serial Number: %d\n", sernum);
+	printf ("%s\n", KAREF_U_BOOT_REL_STR);
+
+	printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
+	if (sbcommon_get_master()) {
+		printf("Slot 0 - Master\nSlave board");
+		if (sbcommon_secondary_present())
+			printf(" present\n");
+		else
+			printf(" not detected\n");
+	} else {
+		printf("Slot 1 - Slave\n\n");
+	}
+
+	printf ("ScanFPGA ID:\t0x%02X\tRev:  0x%02X\n", scan_id, scan_rev);
+	printf ("Board Rev:\t0x%02X\tID:   0x%02X\n", brd_rev, brd_id);
+	if(0xF != ofem_brd_id) {
+		printf("OFemFPGA ID:\t0x%02X\tRev:  0x%02X\n", ofem_id, ofem_rev);
+		printf("OFEM Board Rev:\t0x%02X\tID:   0x%02X\n", ofem_brd_id, ofem_brd_rev);
+	}
+
+	printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+	printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+	printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+	printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
+
+	/* Fix the ack in the bme 32 */
+	udelay(5000);
+	out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
+	asm("eieio");
+
+
+	return (0);
+}
+
+
+/*************************************************************************
+ *  misc_init_f
+ *
+ *  Initialize I2C bus one to gain access to the fans
+ *
+ ************************************************************************/
+int misc_init_f (void)
+{
+	/* Turn on i2c bus 1 */
+	puts ("I2C1:  ");
+	i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	puts ("ready\n");
+
+	/* Turn on fans 3 & 4 */
+	sbcommon_fans();
+
+	return (0);
+}
+/*************************************************************************
+ *  misc_init_r
+ *
+ *  Do nothing.
+ *
+ ************************************************************************/
+int misc_init_r (void)
+{
+	unsigned short sernum;
+	char envstr[255];
+	KAREF_FPGA_REGS_ST *karef_ps;
+	OFEM_FPGA_REGS_ST *ofem_ps;
+	unsigned char ofem_id;
+
+	if(NULL != getenv("secondserial")) {
+		puts("secondserial is set, switching to second serial port\n");
+		setenv("stderr", "serial1");
+		setenv("stdout", "serial1");
+		setenv("stdin", "serial1");
+	}
+
+	setenv("ubrelver", KAREF_U_BOOT_REL_STR);
+
+	memset(envstr, 0, 255);
+	sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
+	setenv("bldstr", envstr);
+	saveenv();
+
+	if( getenv("autorecover")) {
+		setenv("autorecover", NULL);
+		saveenv();
+		sernum = sbcommon_get_serial_number();
+
+		printf("\nSetting up environment for automatic filesystem recovery\n");
+		/*
+		 * Setup default bootargs
+		 */
+		memset(envstr, 0, 255);
+
+		sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
+			"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
+			sernum, sernum);
+		setenv("bootargs", envstr);
+
+		/*
+		 * Setup Default boot command
+		 */
+		setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
+		       "fatload ide 0 8100000 pramdisk;"
+		       "bootm 8000000 8100000");
+
+		printf("Done.  Please type allow the system to continue to boot\n");
+	}
+
+	if( getenv("fakeled")) {
+		karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+		ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
+		ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
+		karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
+		setenv("bootdelay", "-1");
+		saveenv();
+		printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
+	}
+
+
+
+
+	return (0);
+}
+
+
+
+
+/*************************************************************************
+ *  ide_set_reset
+ *
+ *
+ *
+ ************************************************************************/
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+	KAREF_FPGA_REGS_ST *karef_ps;
+	/* TODO: ide reset */
+	karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+
+	if (on) {
+		karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
+	} else {
+		karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+/*************************************************************************
+ *  fpga_init
+ *
+ *
+ *
+ ************************************************************************/
+void fpga_init(void)
+{
+	KAREF_FPGA_REGS_ST *karef_ps;
+	OFEM_FPGA_REGS_ST *ofem_ps;
+	unsigned char ofem_id;
+	unsigned long tmp;
+
+	/* Ensure we have power all around */
+	udelay(500);
+
+	karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+	tmp =
+		SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
+
+	karef_ps->reset_ul = tmp;
+
+	/*
+	 * Wait a bit to allow the ofem fpga to get its brains
+	 */
+	udelay(5000);
+
+	/*
+	 * Check to see if the ofem is there
+	 */
+	ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
+				  >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
+	if(0xF != ofem_id) {
+		tmp =
+			SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
+			SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
+			SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
+
+		ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
+		ofem_ps->reset_ul = tmp;
+
+		ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
+	}
+
+	karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
+
+	asm("eieio");
+
+	return;
+}
+
+
+
+int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned short sernum;
+	char envstr[255];
+
+	sernum = sbcommon_get_serial_number();
+
+	memset(envstr, 0, 255);
+	/*
+	 * Setup our ip address
+	 */
+	sprintf(envstr, "10.100.70.%d", sernum);
+
+	setenv("ipaddr", envstr);
+	/*
+	 * Setup the host ip address
+	 */
+	setenv("serverip", "10.100.17.10");
+
+	/*
+	 * Setup default bootargs
+	 */
+	memset(envstr, 0, 255);
+
+	sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
+		"rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
+		"nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
+		"255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
+		sernum, sernum, sernum);
+
+	setenv("bootargs_nfs", envstr);
+	setenv("bootargs", envstr);
+
+	/*
+	 * Setup CF bootargs
+	 */
+	memset(envstr, 0, 255);
+
+	sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
+		"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
+		sernum, sernum);
+
+	setenv("bootargs_cf", envstr);
+
+	/*
+	 * Setup Default boot command
+	 */
+	setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
+	setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
+
+	/*
+	 * Setup compact flash boot command
+	 */
+	setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
+
+	saveenv();
+
+	return(1);
+}
+
+
+int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned short sernum;
+	char envstr[255];
+
+	sernum = sbcommon_get_serial_number();
+
+	printf("\nSetting up environment for filesystem recovery\n");
+	/*
+	 * Setup default bootargs
+	 */
+	memset(envstr, 0, 255);
+
+	sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
+		"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
+		sernum, sernum);
+	setenv("bootargs", envstr);
+
+	/*
+	 * Setup Default boot command
+	 */
+
+	setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
+	       "fatload ide 0 8100000 pramdisk;"
+	       "bootm 8000000 8100000");
+
+	printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
+	       " please type fsrecover.sh<cr>\n");
+
+	return(1);
+}
+
+
+
+
+
+
+
+U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
+	   "kasetup - Set environment to factory defaults\n", NULL);
+
+U_BOOT_CMD(karecover, 1, 1, karefRecover,
+	   "karecover - Set environment to allow for fs recovery\n", NULL);
+
diff --git a/board/sandburst/karef/karef.h b/board/sandburst/karef/karef.h
new file mode 100644
index 0000000..7790819
--- /dev/null
+++ b/board/sandburst/karef/karef.h
@@ -0,0 +1,76 @@
+#ifndef __KAREF_H__
+#define __KAREF_H__
+/*
+ * (C) Copyright 2005
+ * Sandburst Corporation
+ * Travis B. Sawyer
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Ka Reference Design OFEM FPGA Registers & definitions */
+#include "hal_ka_sc_auto.h"
+#include "hal_ka_of_auto.h"
+
+typedef struct karef_board_id_s {
+	const char name[40];
+} KAREF_BOARD_ID_ST, *KAREF_BOARD_ID_PST;
+
+/* SCAN FPGA */
+typedef struct karef_fpga_regs_s
+{
+    volatile unsigned long revision_ul;       /* Read Only  */
+    volatile unsigned long reset_ul;          /* Read/Write */
+    volatile unsigned long interrupt_ul;      /* Read Only  */
+    volatile unsigned long mask_ul;           /* Read/Write */
+    volatile unsigned long scratch_ul;        /* Read/Write */
+    volatile unsigned long scrmask_ul;        /* Read/Write */
+    volatile unsigned long status_ul;         /* Read Only  */
+    volatile unsigned long control_ul;        /* Read/Write */
+    volatile unsigned long boardinfo_ul;      /* Read Only  */
+    volatile unsigned long scan_from0_ul;     /* Read Only  */
+    volatile unsigned long scan_from1_ul;     /* Read Only  */
+    volatile unsigned long scan_to0_ul;       /* Read/Write */
+    volatile unsigned long scan_to1_ul;       /* Read/Write */
+    volatile unsigned long scan_control_ul;   /* Read/Write */
+    volatile unsigned long pll_control_ul;    /* Read/Write */
+    volatile unsigned long core_clock_cnt_ul; /* Read/Write */
+    volatile unsigned long dr_clock_cnt_ul;   /* Read/Write */
+    volatile unsigned long spi_clock_cnt_ul;  /* Read/Write */
+    volatile unsigned long brdout_data_ul;    /* Read/Write */
+    volatile unsigned long brdout_enable_ul;  /* Read/Write */
+    volatile unsigned long brdin_data_ul;     /* Read Only  */
+    volatile unsigned long misc_ul;           /* Read/Write */
+} KAREF_FPGA_REGS_ST __attribute__((packed)), * KAREF_FPGA_REGS_PST;
+
+/* OFEM FPGA */
+typedef struct ofem_fpga_regs_s
+{
+    volatile unsigned long revision_ul;       /* Read Only  */
+    volatile unsigned long reset_ul;          /* Read/Write */
+    volatile unsigned long interrupt_ul;      /* Read Only  */
+    volatile unsigned long mask_ul;           /* Read/Write */
+    volatile unsigned long scratch_ul;        /* Read/Write */
+    volatile unsigned long scrmask_ul;        /* Read/Write */
+    volatile unsigned long control_ul;        /* Read/Write */
+    volatile unsigned long mac_flow_ctrl_ul;  /* Read/Write */
+} OFEM_FPGA_REGS_ST __attribute__((packed)), * OFEM_FPGA_REGS_PST;
+
+
+#endif /* __KAREF_H__ */
diff --git a/board/sandburst/karef/karef_version.h b/board/sandburst/karef/karef_version.h
new file mode 100644
index 0000000..9960b9a
--- /dev/null
+++ b/board/sandburst/karef/karef_version.h
@@ -0,0 +1,26 @@
+#ifndef _KAREF_VERSION_H_
+#define _KAREF_VERSION_H_
+/*
+ *  Copyright (C) 2005 Sandburst Corporation
+ *  Travis B. Sawyer
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#define KAREF_U_BOOT_REL_STR "Release 0.0.7"
+#endif
diff --git a/board/sandburst/karef/u-boot.lds b/board/sandburst/karef/u-boot.lds
new file mode 100644
index 0000000..ff8658f
--- /dev/null
+++ b/board/sandburst/karef/u-boot.lds
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/sandburst/karef/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/440gx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug
new file mode 100644
index 0000000..c6522b9
--- /dev/null
+++ b/board/sandburst/karef/u-boot.lds.debug
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2002-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/sandburst/karef/init.o (.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/440gx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}