Merge branch 'master' of /home/stefan/git/u-boot/u-boot into next

1 files changed, 31 insertions, 19 deletions

diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c
index 2d71d3b..72ce976 100644
--- a/board/sandburst/karef/karef.c
+++ b/board/sandburst/karef/karef.c
@@ -195,36 +195,48 @@ int board_early_init_f (void)
 	/*--------------------------------------------------------------------+
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 +-------------------------------------------------------------------*/
-	mtdcr (uic0sr, 0xffffffff);	/* clear all */
-	mtdcr (uic0er, 0x00000000);	/* disable all */
-	mtdcr (uic0cr, 0x00000000);	/* all non- critical */
-	mtdcr (uic0pr, 0xfffffe03);	/* polarity */
-	mtdcr (uic0tr, 0x01c00000);	/* trigger edge vs level */
-	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic0sr, 0xffffffff);	/* clear all */
-
+	/*
+	 * Because of the interrupt handling rework to handle 440GX interrupts
+	 * with the common code, we needed to change names of the UIC registers.
+	 * Here the new relationship:
+	 *
+	 * U-Boot name	440GX name
+	 * -----------------------
+	 * UIC0		UICB0
+	 * UIC1		UIC0
+	 * UIC2		UIC1
+	 * UIC3		UIC2
+	 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 	mtdcr (uic1er, 0x00000000);	/* disable all */
-	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic1pr, 0xffffc8ff);	/* polarity */
-	mtdcr (uic1tr, 0x00ff0000);	/* trigger edge vs level */
+	mtdcr (uic1cr, 0x00000000);	/* all non- critical */
+	mtdcr (uic1pr, 0xfffffe03);	/* polarity */
+	mtdcr (uic1tr, 0x01c00000);	/* trigger edge vs level */
 	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 
 	mtdcr (uic2sr, 0xffffffff);	/* clear all */
 	mtdcr (uic2er, 0x00000000);	/* disable all */
 	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic2pr, 0xffff83ff);	/* polarity */
-	mtdcr (uic2tr, 0x00ff8c0f);	/* trigger edge vs level */
+	mtdcr (uic2pr, 0xffffc8ff);	/* polarity */
+	mtdcr (uic2tr, 0x00ff0000);	/* trigger edge vs level */
 	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic2sr, 0xffffffff);	/* clear all */
 
-	mtdcr (uicb0sr, 0xfc000000);	/* clear all */
-	mtdcr (uicb0er, 0x00000000);	/* disable all */
-	mtdcr (uicb0cr, 0x00000000);	/* all non-critical */
-	mtdcr (uicb0pr, 0xfc000000);
-	mtdcr (uicb0tr, 0x00000000);
-	mtdcr (uicb0vr, 0x00000001);
+	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+	mtdcr (uic3er, 0x00000000);	/* disable all */
+	mtdcr (uic3cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic3pr, 0xffff83ff);	/* polarity */
+	mtdcr (uic3tr, 0x00ff8c0f);	/* trigger edge vs level */
+	mtdcr (uic3vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic0sr, 0xfc000000);	/* clear all */
+	mtdcr (uic0er, 0x00000000);	/* disable all */
+	mtdcr (uic0cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic0pr, 0xfc000000);
+	mtdcr (uic0tr, 0x00000000);
+	mtdcr (uic0vr, 0x00000001);
 
 	fpga_init();