EXYNOS: Add SMDK5250 board support

SMDK5250 board is based on Samsungs EXYNOS5250 SoC.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

7 files changed, 1456 insertions, 0 deletions

diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
new file mode 100644
index 0000000..80e8be3
--- /dev/null
+++ b/board/samsung/smdk5250/Makefile
@@ -0,0 +1,51 @@
+#
+# Copyright (C) 2012 Samsung Electronics
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+SOBJS	:= lowlevel_init.o
+
+COBJS	:= clock_init.o
+COBJS	+= dmc_init.o
+COBJS	+= tzpc_init.o
+COBJS	+= smdk5250.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+ALL	:=	 $(obj).depend $(LIB)
+
+all:	$(ALL)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c
new file mode 100644
index 0000000..305842d
--- /dev/null
+++ b/board/samsung/smdk5250/clock_init.c
@@ -0,0 +1,202 @@
+/*
+ * Clock setup for SMDK5250 board based on EXYNOS5
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include "setup.h"
+
+void system_clock_init()
+{
+	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+
+	/*
+	 * MUX_APLL_SEL[0]: FINPLL = 0
+	 * MUX_CPU_SEL[6]: MOUTAPLL = 0
+	 * MUX_HPM_SEL[20]: MOUTAPLL = 0
+	 */
+	writel(0x0, &clk->src_cpu);
+
+	/* MUX_MPLL_SEL[8]: FINPLL = 0 */
+	writel(0x0, &clk->src_core1);
+
+	/*
+	 * VPLLSRC_SEL[0]: FINPLL = 0
+	 * MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: FINPLL = 0
+	 */
+	writel(0x0, &clk->src_top2);
+
+	/* MUX_BPLL_SEL[0]: FINPLL = 0 */
+	writel(0x0, &clk->src_cdrex);
+
+	/* MUX_ACLK_* Clock Selection */
+	writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+
+	/* MUX_ACLK_* Clock Selection */
+	writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+
+	/* MUX_ACLK_* Clock Selection */
+	writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
+
+	/* MUX_PWI_SEL[19:16]: SCLKMPLL = 6 */
+	writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
+
+	/* MUX_ATCLK_LEX[0]: ACLK_200 = 0 */
+	writel(CLK_SRC_LEX_VAL, &clk->src_lex);
+
+	/* UART [0-5]: SCLKMPLL = 6 */
+	writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
+
+	/* Set Clock Ratios */
+	writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
+
+	/* Set COPY and HPM Ratio */
+	writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
+
+	/* CORED_RATIO, COREP_RATIO */
+	writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
+
+	/* PWI_RATIO[11:8], DVSEM_RATIO[22:16], DPM_RATIO[24:20] */
+	writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
+
+	/* ACLK_*_RATIO */
+	writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
+
+	/* ACLK_*_RATIO */
+	writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
+
+	/* CDREX Ratio */
+	writel(CLK_DIV_CDREX_INIT_VAL, &clk->div_cdrex);
+
+	/* MCLK_EFPHY_RATIO[3:0] */
+	writel(CLK_DIV_CDREX2_VAL, &clk->div_cdrex2);
+
+	/* {PCLK[4:6]|ATCLK[10:8]}_RATIO */
+	writel(CLK_DIV_LEX_VAL, &clk->div_lex);
+
+	/* PCLK_R0X_RATIO[3:0] */
+	writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
+
+	/* PCLK_R1X_RATIO[3:0] */
+	writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
+
+	/* SATA[24]: SCLKMPLL=0, MMC[0-4]: SCLKMPLL = 6 */
+	writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
+
+	/* UART[0-4] */
+	writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
+
+	/* PWM_RATIO[3:0] */
+	writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
+
+	/* SATA_RATIO, USB_DRD_RATIO */
+	writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
+
+	/* MMC[0-1] */
+	writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
+
+	/* MMC[2-3] */
+	writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
+
+	/* MMC[4] */
+	writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
+
+	/* ACLK|PLCK_ACP_RATIO */
+	writel(CLK_DIV_ACP_VAL, &clk->div_acp);
+
+	/* ISPDIV0_RATIO, ISPDIV1_RATIO */
+	writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
+
+	/* MCUISPDIV0_RATIO, MCUISPDIV1_RATIO */
+	writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
+
+	/* MPWMDIV_RATIO */
+	writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
+
+	/* PLL locktime */
+	writel(APLL_LOCK_VAL, &clk->apll_lock);
+
+	writel(MPLL_LOCK_VAL, &clk->mpll_lock);
+
+	writel(BPLL_LOCK_VAL, &clk->bpll_lock);
+
+	writel(CPLL_LOCK_VAL, &clk->cpll_lock);
+
+	writel(EPLL_LOCK_VAL, &clk->epll_lock);
+
+	writel(VPLL_LOCK_VAL, &clk->vpll_lock);
+
+	sdelay(0x10000);
+
+	/* Set APLL */
+	writel(APLL_CON1_VAL, &clk->apll_con1);
+	writel(APLL_CON0_VAL, &clk->apll_con0);
+	sdelay(0x30000);
+
+	/* Set MPLL */
+	writel(MPLL_CON1_VAL, &clk->mpll_con1);
+	writel(MPLL_CON0_VAL, &clk->mpll_con0);
+	sdelay(0x30000);
+	writel(BPLL_CON1_VAL, &clk->bpll_con1);
+	writel(BPLL_CON0_VAL, &clk->bpll_con0);
+	sdelay(0x30000);
+
+	/* Set CPLL */
+	writel(CPLL_CON1_VAL, &clk->cpll_con1);
+	writel(CPLL_CON0_VAL, &clk->cpll_con0);
+	sdelay(0x30000);
+
+	/* Set EPLL */
+	writel(EPLL_CON2_VAL, &clk->epll_con2);
+	writel(EPLL_CON1_VAL, &clk->epll_con1);
+	writel(EPLL_CON0_VAL, &clk->epll_con0);
+	sdelay(0x30000);
+
+	/* Set VPLL */
+	writel(VPLL_CON2_VAL, &clk->vpll_con2);
+	writel(VPLL_CON1_VAL, &clk->vpll_con1);
+	writel(VPLL_CON0_VAL, &clk->vpll_con0);
+	sdelay(0x30000);
+
+	/* Set MPLL */
+	/* After Initiallising th PLL select the sources accordingly */
+	/* MUX_APLL_SEL[0]: MOUTAPLLFOUT = 1 */
+	writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
+
+	/* MUX_MPLL_SEL[8]: MOUTMPLLFOUT = 1 */
+	writel(CLK_SRC_CORE1_VAL, &clk->src_core1);
+
+	/* MUX_BPLL_SEL[0]: FOUTBPLL = 1*/
+	writel(CLK_SRC_CDREX_INIT_VAL, &clk->src_cdrex);
+
+	/*
+	 * VPLLSRC_SEL[0]: FINPLL = 0
+	 * MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: MOUT{CPLL|EPLL|VPLL} = 1
+	 * MUX_{MPLL[20]}|{BPLL[24]}_USER_SEL: FOUT{MPLL|BPLL} = 1
+	 */
+	writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
+}
diff --git a/board/samsung/smdk5250/dmc_init.c b/board/samsung/smdk5250/dmc_init.c
new file mode 100644
index 0000000..7881074
--- /dev/null
+++ b/board/samsung/smdk5250/dmc_init.c
@@ -0,0 +1,462 @@
+/*
+ * Memory setup for SMDK5250 board based on EXYNOS5
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/dmc.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include "setup.h"
+
+/* APLL : 1GHz */
+/* MCLK_CDREX: MCLK_CDREX_533*/
+/* LPDDR support: LPDDR2 */
+static void reset_phy_ctrl(void);
+static void config_zq(struct exynos5_phy_control *,
+			struct exynos5_phy_control *);
+static void update_reset_dll(struct exynos5_dmc *);
+static void config_cdrex(void);
+static void config_mrs(struct exynos5_dmc *);
+static void sec_sdram_phy_init(struct exynos5_dmc *);
+static void config_prech(struct exynos5_dmc *);
+static void config_rdlvl(struct exynos5_dmc *,
+			struct exynos5_phy_control *,
+			struct exynos5_phy_control *);
+static void config_memory(struct exynos5_dmc *);
+
+static void config_offsets(unsigned int,
+				struct exynos5_phy_control *,
+				struct exynos5_phy_control *);
+
+static void reset_phy_ctrl(void)
+{
+	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+
+	writel(PHY_RESET_VAL, &clk->lpddr3phy_ctrl);
+	sdelay(0x10000);
+}
+
+static void config_zq(struct exynos5_phy_control *phy0_ctrl,
+			struct exynos5_phy_control *phy1_ctrl)
+{
+	unsigned long val = 0;
+	/*
+	 * ZQ Calibration:
+	 * Select Driver Strength,
+	 * long calibration for manual calibration
+	 */
+	val = PHY_CON16_RESET_VAL;
+	SET_ZQ_MODE_DDS_VAL(val);
+	SET_ZQ_MODE_TERM_VAL(val);
+	val |= ZQ_CLK_DIV_EN;
+	writel(val, &phy0_ctrl->phy_con16);
+	writel(val, &phy1_ctrl->phy_con16);
+
+	/* Disable termination */
+	val |= ZQ_MODE_NOTERM;
+	writel(val, &phy0_ctrl->phy_con16);
+	writel(val, &phy1_ctrl->phy_con16);
+
+	/* ZQ_MANUAL_START: Enable */
+	val |= ZQ_MANUAL_STR;
+	writel(val, &phy0_ctrl->phy_con16);
+	writel(val, &phy1_ctrl->phy_con16);
+	sdelay(0x10000);
+
+	/* ZQ_MANUAL_START: Disable */
+	val &= ~ZQ_MANUAL_STR;
+	writel(val, &phy0_ctrl->phy_con16);
+	writel(val, &phy1_ctrl->phy_con16);
+}
+
+static void update_reset_dll(struct exynos5_dmc *dmc)
+{
+	unsigned long val;
+	/*
+	 * Update DLL Information:
+	 * Force DLL Resyncronization
+	 */
+	val = readl(&dmc->phycontrol0);
+	val |= FP_RSYNC;
+	writel(val, &dmc->phycontrol0);
+
+	/* Reset Force DLL Resyncronization */
+	val = readl(&dmc->phycontrol0);
+	val &= ~FP_RSYNC;
+	writel(val, &dmc->phycontrol0);
+}
+
+static void config_mrs(struct exynos5_dmc *dmc)
+{
+	unsigned long channel, chip, mask = 0, val;
+
+	for (channel = 0; channel < CONFIG_DMC_CHANNELS; channel++) {
+		SET_CMD_CHANNEL(mask, channel);
+		for (chip = 0; chip < CONFIG_CHIPS_PER_CHANNEL; chip++) {
+			/*
+			 * NOP CMD:
+			 * Assert and hold CKE to logic high level
+			 */
+			SET_CMD_CHIP(mask, chip);
+			val = DIRECT_CMD_NOP | mask;
+			writel(val, &dmc->directcmd);
+			sdelay(0x10000);
+
+			/* EMRS, MRS Cmds(Mode Reg Settings) Using Direct Cmd */
+			val = DIRECT_CMD_MRS1 | mask;
+			writel(val, &dmc->directcmd);
+			sdelay(0x10000);
+
+			val = DIRECT_CMD_MRS2 | mask;
+			writel(val, &dmc->directcmd);
+			sdelay(0x10000);
+
+			/* MCLK_CDREX_533 */
+			val = DIRECT_CMD_MRS3 | mask;
+			writel(val, &dmc->directcmd);
+			sdelay(0x10000);
+
+			val = DIRECT_CMD_MRS4 | mask;
+			writel(val, &dmc->directcmd);
+			sdelay(0x10000);
+		}
+	}
+}
+
+static void config_prech(struct exynos5_dmc *dmc)
+{
+	unsigned long channel, chip, mask = 0, val;
+
+	for (channel = 0; channel < CONFIG_DMC_CHANNELS; channel++) {
+		SET_CMD_CHANNEL(mask, channel);
+		for (chip = 0; chip < CONFIG_CHIPS_PER_CHANNEL; chip++) {
+			SET_CMD_CHIP(mask, chip);
+			/* PALL (all banks precharge) CMD */
+			val = DIRECT_CMD_PALL | mask;
+			writel(val, &dmc->directcmd);
+			sdelay(0x10000);
+		}
+	}
+}
+
+static void sec_sdram_phy_init(struct exynos5_dmc *dmc)
+{
+	unsigned long val;
+	val = readl(&dmc->concontrol);
+	val |= DFI_INIT_START;
+	writel(val, &dmc->concontrol);
+	sdelay(0x10000);
+
+	val = readl(&dmc->concontrol);
+	val &= ~DFI_INIT_START;
+	writel(val, &dmc->concontrol);
+}
+
+static void config_offsets(unsigned int state,
+				struct exynos5_phy_control *phy0_ctrl,
+				struct exynos5_phy_control *phy1_ctrl)
+{
+	unsigned long val;
+	/* Set Offsets to read DQS */
+	val = (state == SET) ? SET_DQS_OFFSET_VAL : RESET_DQS_OFFSET_VAL;
+	writel(val, &phy0_ctrl->phy_con4);
+	writel(val, &phy1_ctrl->phy_con4);
+
+	/* Set Offsets to read DQ */
+	val = (state == SET) ? SET_DQ_OFFSET_VAL : RESET_DQ_OFFSET_VAL;
+	writel(val, &phy0_ctrl->phy_con6);
+	writel(val, &phy1_ctrl->phy_con6);
+
+	/* Debug Offset */
+	val = (state == SET) ? SET_DEBUG_OFFSET_VAL : RESET_DEBUG_OFFSET_VAL;
+	writel(val, &phy0_ctrl->phy_con10);
+	writel(val, &phy1_ctrl->phy_con10);
+}
+
+static void config_cdrex(void)
+{
+	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+	writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
+	writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
+	sdelay(0x30000);
+}
+
+static void config_ctrl_dll_on(unsigned int state,
+			unsigned int ctrl_force_val,
+			struct exynos5_phy_control *phy0_ctrl,
+			struct exynos5_phy_control *phy1_ctrl)
+{
+	unsigned long val;
+	val = readl(&phy0_ctrl->phy_con12);
+	CONFIG_CTRL_DLL_ON(val, state);
+	SET_CTRL_FORCE_VAL(val, ctrl_force_val);
+	writel(val, &phy0_ctrl->phy_con12);
+
+	val = readl(&phy1_ctrl->phy_con12);
+	CONFIG_CTRL_DLL_ON(val, state);
+	SET_CTRL_FORCE_VAL(val, ctrl_force_val);
+	writel(val, &phy1_ctrl->phy_con12);
+}
+
+static void config_ctrl_start(unsigned int state,
+			struct exynos5_phy_control *phy0_ctrl,
+			struct exynos5_phy_control *phy1_ctrl)
+{
+	unsigned long val;
+	val = readl(&phy0_ctrl->phy_con12);
+	CONFIG_CTRL_START(val, state);
+	writel(val, &phy0_ctrl->phy_con12);
+
+	val = readl(&phy1_ctrl->phy_con12);
+	CONFIG_CTRL_START(val, state);
+	writel(val, &phy1_ctrl->phy_con12);
+}
+
+#if defined(CONFIG_RD_LVL)
+static void config_rdlvl(struct exynos5_dmc *dmc,
+			struct exynos5_phy_control *phy0_ctrl,
+			struct exynos5_phy_control *phy1_ctrl)
+{
+	unsigned long val;
+
+	/* Disable CTRL_DLL_ON and set ctrl_force */
+	config_ctrl_dll_on(RESET, 0x2D, phy0_ctrl, phy1_ctrl);
+
+	/*
+	 * Set ctrl_gateadj, ctrl_readadj
+	 * ctrl_gateduradj, rdlvl_pass_adj
+	 * rdlvl_rddataPadj
+	 */
+	val = SET_RDLVL_RDDATAPADJ;
+	writel(val, &phy0_ctrl->phy_con1);
+	writel(val, &phy1_ctrl->phy_con1);
+
+	/* LPDDR2 Address */
+	writel(LPDDR2_ADDR, &phy0_ctrl->phy_con22);
+	writel(LPDDR2_ADDR, &phy1_ctrl->phy_con22);
+
+	/* Enable Byte Read Leveling set ctrl_ddr_mode */
+	val = readl(&phy0_ctrl->phy_con0);
+	val |= BYTE_RDLVL_EN;
+	writel(val, &phy0_ctrl->phy_con0);
+	val = readl(&phy1_ctrl->phy_con0);
+	val |= BYTE_RDLVL_EN;
+	writel(val, &phy1_ctrl->phy_con0);
+
+	/* rdlvl_en: Use levelling offset instead ctrl_shiftc */
+	val = PHY_CON2_RESET_VAL | RDLVL_EN;
+	writel(val, &phy0_ctrl->phy_con2);
+	writel(val, &phy1_ctrl->phy_con2);
+	sdelay(0x10000);
+
+	/* Enable Data Eye Training */
+	val = readl(&dmc->rdlvl_config);
+	val |= CTRL_RDLVL_DATA_EN;
+	writel(val, &dmc->rdlvl_config);
+	sdelay(0x10000);
+
+	/* Disable Data Eye Training */
+	val = readl(&dmc->rdlvl_config);
+	val &= ~CTRL_RDLVL_DATA_EN;
+	writel(val, &dmc->rdlvl_config);
+
+	/* RdDeSkew_clear: Clear */
+	val = readl(&phy0_ctrl->phy_con2);
+	val |= RDDSKEW_CLEAR;
+	writel(val, &phy0_ctrl->phy_con2);
+	val = readl(&phy1_ctrl->phy_con2);
+	val |= RDDSKEW_CLEAR;
+	writel(val, &phy1_ctrl->phy_con2);
+
+	/* Enable CTRL_DLL_ON */
+	config_ctrl_dll_on(SET, 0x0, phy0_ctrl, phy1_ctrl);
+
+	update_reset_dll(dmc);
+	sdelay(0x10000);
+
+	/* ctrl_atgte: ctrl_gate_p*, ctrl_read_p* generated by PHY */
+	val = readl(&phy0_ctrl->phy_con0);
+	val &= ~CTRL_ATGATE;
+	writel(val, &phy0_ctrl->phy_con0);
+	val = readl(&phy1_ctrl->phy_con0);
+	val &= ~CTRL_ATGATE;
+	writel(val, &phy1_ctrl->phy_con0);
+}
+#endif
+
+static void config_memory(struct exynos5_dmc *dmc)
+{
+	/*
+	 * Memory Configuration Chip 0
+	 * Address Mapping: Interleaved
+	 * Number of Column address Bits: 10 bits
+	 * Number of Rows Address Bits: 14
+	 * Number of Banks: 8
+	 */
+	writel(DMC_MEMCONFIG0_VAL, &dmc->memconfig0);
+
+	/*
+	 * Memory Configuration Chip 1
+	 * Address Mapping: Interleaved
+	 * Number of Column address Bits: 10 bits
+	 * Number of Rows Address Bits: 14
+	 * Number of Banks: 8
+	 */
+	writel(DMC_MEMCONFIG1_VAL, &dmc->memconfig1);
+
+	/*
+	 * Chip0: AXI
+	 * AXI Base Address: 0x40000000
+	 * AXI Base Address Mask: 0x780
+	 */
+	writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
+
+	/*
+	 * Chip1: AXI
+	 * AXI Base Address: 0x80000000
+	 * AXI Base Address Mask: 0x780
+	 */
+	writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
+}
+
+void mem_ctrl_init()
+{
+	struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
+	struct exynos5_dmc *dmc;
+	unsigned long val;
+
+	phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
+	phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
+	dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
+
+	/* Reset PHY Controllor: PHY_RESET[0] */
+	reset_phy_ctrl();
+
+	/*set Read Latancy and Burst Length for PHY0 and PHY1 */
+	writel(PHY_CON42_VAL, &phy0_ctrl->phy_con42);
+	writel(PHY_CON42_VAL, &phy1_ctrl->phy_con42);
+
+	/* ZQ Cofiguration */
+	config_zq(phy0_ctrl, phy1_ctrl);
+
+	/* Operation Mode : LPDDR2 */
+	val = PHY_CON0_RESET_VAL;
+	SET_CTRL_DDR_MODE(val, DDR_MODE_LPDDR2);
+	writel(val, &phy0_ctrl->phy_con0);
+	writel(val, &phy1_ctrl->phy_con0);
+
+	/* DQS, DQ: Signal, for LPDDR2: Always Set */
+	val = CTRL_PULLD_DQ | CTRL_PULLD_DQS;
+	writel(val, &phy0_ctrl->phy_con14);
+	writel(val, &phy1_ctrl->phy_con14);
+
+	/* Init SEC SDRAM PHY */
+	sec_sdram_phy_init(dmc);
+	sdelay(0x10000);
+
+	update_reset_dll(dmc);
+
+	/*
+	 * Dynamic Clock: Always Running
+	 * Memory Burst length: 4
+	 * Number of chips: 2
+	 * Memory Bus width: 32 bit
+	 * Memory Type: LPDDR2-S4
+	 * Additional Latancy for PLL: 1 Cycle
+	 */
+	writel(DMC_MEMCONTROL_VAL, &dmc->memcontrol);
+
+	config_memory(dmc);
+
+	/* Precharge Configuration */
+	writel(DMC_PRECHCONFIG_VAL, &dmc->prechconfig);
+
+	/* Power Down mode Configuration */
+	writel(DMC_PWRDNCONFIG_VAL, &dmc->pwrdnconfig);
+
+	/* Periodic Refrese Interval */
+	writel(DMC_TIMINGREF_VAL, &dmc->timingref);
+
+	/*
+	 * TimingRow, TimingData, TimingPower Setting:
+	 * Values as per Memory AC Parameters
+	 */
+	writel(DMC_TIMINGROW_VAL, &dmc->timingrow);
+
+	writel(DMC_TIMINGDATA_VAL, &dmc->timingdata);
+
+	writel(DMC_TIMINGPOWER_VAL, &dmc->timingpower);
+
+	/* Memory Channel Inteleaving Size: 128 Bytes */
+	writel(CONFIG_IV_SIZE, &dmc->ivcontrol);
+
+	/* Set DQS, DQ and DEBUG offsets */
+	config_offsets(SET, phy0_ctrl, phy1_ctrl);
+
+	/* Disable CTRL_DLL_ON and set ctrl_force */
+	config_ctrl_dll_on(RESET, 0x7F, phy0_ctrl, phy1_ctrl);
+	sdelay(0x10000);
+
+	update_reset_dll(dmc);
+
+	/* Config MRS(Mode Register Settingg) */
+	config_mrs(dmc);
+
+	config_cdrex();
+
+	/* Reset DQS DQ and DEBUG offsets */
+	config_offsets(RESET, phy0_ctrl, phy1_ctrl);
+
+	/* Enable CTRL_DLL_ON */
+	config_ctrl_dll_on(SET, 0x0, phy0_ctrl, phy1_ctrl);
+
+	/* Stop DLL Locking */
+	config_ctrl_start(RESET, phy0_ctrl, phy1_ctrl);
+	sdelay(0x10000);
+
+	/* Start DLL Locking */
+	config_ctrl_start(SET, phy0_ctrl, phy1_ctrl);
+	sdelay(0x10000);
+
+	update_reset_dll(dmc);
+
+#if defined(CONFIG_RD_LVL)
+	config_rdlvl(dmc, phy0_ctrl, phy1_ctrl);
+#endif
+	config_prech(dmc);
+
+	/*
+	 * Dynamic Clock: Stops During Idle Period
+	 * Dynamic Power Down: Enable
+	 * Dynamic Self refresh: Enable
+	 */
+	val = readl(&dmc->memcontrol);
+	val |= CLK_STOP_EN | DPWRDN_EN | DSREF_EN;
+	writel(val, &dmc->memcontrol);
+
+	/* Start Auto refresh */
+	val = readl(&dmc->concontrol);
+	val |= AREF_EN;
+	writel(val, &dmc->concontrol);
+}
diff --git a/board/samsung/smdk5250/lowlevel_init.S b/board/samsung/smdk5250/lowlevel_init.S
new file mode 100644
index 0000000..bc6cb6f
--- /dev/null
+++ b/board/samsung/smdk5250/lowlevel_init.S
@@ -0,0 +1,96 @@
+/*
+ * Lowlevel setup for SMDK5250 board based on S5PC520
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+	.globl lowlevel_init
+lowlevel_init:
+
+	/* use iRAM stack in bl2 */
+	ldr	sp, =CONFIG_IRAM_STACK
+	stmdb	r13!, {ip,lr}
+
+	/* check reset status */
+	ldr	r0, =(EXYNOS5_POWER_BASE + INFORM1_OFFSET)
+	ldr	r1, [r0]
+
+	/* AFTR wakeup reset */
+	ldr	r2, =S5P_CHECK_DIDLE
+	cmp	r1, r2
+	beq	exit_wakeup
+
+	/* LPA wakeup reset */
+	ldr	r2, =S5P_CHECK_LPA
+	cmp	r1, r2
+	beq	exit_wakeup
+
+	/* Sleep wakeup reset */
+	ldr	r2, =S5P_CHECK_SLEEP
+	cmp	r1, r2
+	beq	wakeup_reset
+
+	/*
+	 * If U-boot is already running in RAM, no need to relocate U-Boot.
+	 * Memory controller must be configured before relocating U-Boot
+	 * in ram.
+	 */
+	ldr	r0, =0x0ffffff		/* r0 <- Mask Bits*/
+	bic	r1, pc, r0		/* pc <- current addr of code */
+					/* r1 <- unmasked bits of pc */
+	ldr	r2, _TEXT_BASE		/* r2 <- original base addr in ram */
+	bic	r2, r2, r0		/* r2 <- unmasked bits of r2*/
+	cmp	r1, r2			/* compare r1, r2 */
+	beq	1f			/* r0 == r1 then skip sdram init */
+
+	/* init system clock */
+	bl	system_clock_init
+
+	/* Memory initialize */
+	bl	mem_ctrl_init
+
+1:
+	bl	tzpc_init
+	ldmia	r13!, {ip,pc}
+
+wakeup_reset:
+	bl	system_clock_init
+	bl	mem_ctrl_init
+	bl	tzpc_init
+
+exit_wakeup:
+	/* Load return address and jump to kernel */
+	ldr	r0, =(EXYNOS5_POWER_BASE + INFORM0_OFFSET)
+
+	/* r1 = physical address of exynos5_cpu_resume function*/
+	ldr	r1, [r0]
+
+	/* Jump to kernel */
+	mov	pc, r1
+	nop
+	nop
diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h
new file mode 100644
index 0000000..1276fd3
--- /dev/null
+++ b/board/samsung/smdk5250/setup.h
@@ -0,0 +1,451 @@
+/*
+ * Machine Specific Values for SMDK5250 board based on S5PC520
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SMDK5250_SETUP_H
+#define _SMDK5250_SETUP_H
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+
+/* GPIO Offsets for UART: GPIO Contol Register */
+#define EXYNOS5_GPIO_A0_CON_OFFSET	0x0
+#define EXYNOS5_GPIO_A1_CON_OFFSET	0x20
+
+/* TZPC : Register Offsets */
+#define TZPC0_BASE		0x10100000
+#define TZPC1_BASE		0x10110000
+#define TZPC2_BASE		0x10120000
+#define TZPC3_BASE		0x10130000
+#define TZPC4_BASE		0x10140000
+#define TZPC5_BASE		0x10150000
+#define TZPC6_BASE		0x10160000
+#define TZPC7_BASE		0x10170000
+#define TZPC8_BASE		0x10180000
+#define TZPC9_BASE		0x10190000
+
+/* CLK_SRC_CPU */
+/* 0 = MOUTAPLL, 1 = SCLKMPLL */
+#define MUX_HPM_SEL		0
+#define MUX_CPU_SEL		0
+#define MUX_APLL_SEL		1
+#define CLK_SRC_CPU_VAL		((MUX_HPM_SEL << 20) \
+				| (MUX_CPU_SEL << 16) \
+				| (MUX_APLL_SEL))
+
+/* CLK_DIV_CPU0 */
+#define ARM2_RATIO		0x0
+#define APLL_RATIO		0x1
+#define PCLK_DBG_RATIO		0x1
+#define ATB_RATIO		0x4
+#define PERIPH_RATIO		0x7
+#define ACP_RATIO		0x7
+#define CPUD_RATIO		0x2
+#define ARM_RATIO		0x0
+#define CLK_DIV_CPU0_VAL	((ARM2_RATIO << 28) \
+				| (APLL_RATIO << 24) \
+				| (PCLK_DBG_RATIO << 20) \
+				| (ATB_RATIO << 16) \
+				| (PERIPH_RATIO << 12) \
+				| (ACP_RATIO << 8) \
+				| (CPUD_RATIO << 4) \
+				| (ARM_RATIO))
+
+/* CLK_DIV_CPU1 */
+#define HPM_RATIO		0x4
+#define COPY_RATIO		0x0
+#define CLK_DIV_CPU1_VAL	((HPM_RATIO << 4) \
+				| (COPY_RATIO))
+
+#define APLL_MDIV		0x7D
+#define APLL_PDIV		0x3
+#define APLL_SDIV		0x0
+
+#define MPLL_MDIV		0x64
+#define MPLL_PDIV		0x3
+#define MPLL_SDIV		0x0
+
+#define CPLL_MDIV		0x96
+#define CPLL_PDIV		0x4
+#define CPLL_SDIV		0x0
+
+/* APLL_CON1 */
+#define APLL_CON1_VAL	(0x00203800)
+
+/* MPLL_CON1 */
+#define MPLL_CON1_VAL	(0x00203800)
+
+/* CPLL_CON1 */
+#define CPLL_CON1_VAL	(0x00203800)
+
+#define EPLL_MDIV	0x60
+#define EPLL_PDIV	0x3
+#define EPLL_SDIV	0x3
+
+#define EPLL_CON1_VAL	0x00000000
+#define EPLL_CON2_VAL	0x00000080
+
+#define VPLL_MDIV	0x96
+#define VPLL_PDIV	0x3
+#define VPLL_SDIV	0x2
+
+#define VPLL_CON1_VAL	0x00000000
+#define VPLL_CON2_VAL	0x00000080
+
+#define BPLL_MDIV	0x215
+#define BPLL_PDIV	0xC
+#define BPLL_SDIV	0x1
+
+#define BPLL_CON1_VAL	0x00203800
+
+/* Set PLL */
+#define set_pll(mdiv, pdiv, sdiv)	(1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
+
+#define APLL_CON0_VAL	set_pll(APLL_MDIV, APLL_PDIV, APLL_SDIV)
+#define MPLL_CON0_VAL	set_pll(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
+#define CPLL_CON0_VAL	set_pll(CPLL_MDIV, CPLL_PDIV, CPLL_SDIV)
+#define EPLL_CON0_VAL	set_pll(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
+#define VPLL_CON0_VAL	set_pll(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
+#define BPLL_CON0_VAL	set_pll(BPLL_MDIV, BPLL_PDIV, BPLL_SDIV)
+
+/* CLK_SRC_CORE0 */
+#define CLK_SRC_CORE0_VAL	0x00060000
+
+/* CLK_SRC_CORE1 */
+#define CLK_SRC_CORE1_VAL	0x100
+
+/* CLK_DIV_CORE0 */
+#define CLK_DIV_CORE0_VAL	0x120000
+
+/* CLK_DIV_CORE1 */
+#define CLK_DIV_CORE1_VAL	0x07070700
+
+/* CLK_SRC_CDREX */
+#define CLK_SRC_CDREX_INIT_VAL	0x1
+#define CLK_SRC_CDREX_VAL	0x111
+
+/* CLK_DIV_CDREX */
+#define CLK_DIV_CDREX_INIT_VAL	0x71771111
+
+#define MCLK_CDREX2_RATIO	0x0
+#define ACLK_EFCON_RATIO	0x1
+#define MCLK_DPHY_RATIO		0x0
+#define MCLK_CDREX_RATIO	0x0
+#define ACLK_C2C_200_RATIO	0x1
+#define C2C_CLK_400_RATIO	0x1
+#define PCLK_CDREX_RATIO	0x3
+#define ACLK_CDREX_RATIO	0x1
+#define CLK_DIV_CDREX_VAL	((MCLK_DPHY_RATIO << 20) \
+				| (MCLK_CDREX_RATIO << 16) \
+				| (ACLK_C2C_200_RATIO << 12) \
+				| (C2C_CLK_400_RATIO << 8) \
+				| (PCLK_CDREX_RATIO << 4) \
+				| (ACLK_CDREX_RATIO))
+
+#define MCLK_EFPHY_RATIO	0x4
+#define CLK_DIV_CDREX2_VAL	MCLK_EFPHY_RATIO
+
+/* CLK_DIV_ACP */
+#define CLK_DIV_ACP_VAL	0x12
+
+/* CLK_SRC_TOP0 */
+#define MUX_ACLK_300_GSCL_SEL		0x1
+#define MUX_ACLK_300_GSCL_MID_SEL	0x0
+#define MUX_ACLK_400_SEL		0x0
+#define MUX_ACLK_333_SEL		0x0
+#define MUX_ACLK_300_DISP1_SEL		0x1
+#define MUX_ACLK_300_DISP1_MID_SEL	0x0
+#define MUX_ACLK_200_SEL		0x0
+#define MUX_ACLK_166_SEL		0x0
+#define CLK_SRC_TOP0_VAL	((MUX_ACLK_300_GSCL_SEL << 25) \
+				| (MUX_ACLK_300_GSCL_MID_SEL << 24) \
+				| (MUX_ACLK_400_SEL << 20) \
+				| (MUX_ACLK_333_SEL << 16) \
+				| (MUX_ACLK_300_DISP1_SEL << 15) \
+				| (MUX_ACLK_300_DISP1_MID_SEL << 14)	\
+				| (MUX_ACLK_200_SEL << 12) \
+				| (MUX_ACLK_166_SEL << 8))
+
+/* CLK_SRC_TOP1 */
+#define MUX_ACLK_400_ISP_SEL		0x0
+#define MUX_ACLK_400_IOP_SEL		0x0
+#define MUX_ACLK_MIPI_HSI_TXBASE_SEL	0x0
+#define CLK_SRC_TOP1_VAL		((MUX_ACLK_400_ISP_SEL << 24) \
+					|(MUX_ACLK_400_IOP_SEL << 20) \
+					|(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16))
+
+/* CLK_SRC_TOP2 */
+#define MUX_BPLL_USER_SEL	0x1
+#define MUX_MPLL_USER_SEL	0x1
+#define MUX_VPLL_SEL		0x0
+#define MUX_EPLL_SEL		0x0
+#define MUX_CPLL_SEL		0x0
+#define VPLLSRC_SEL		0x0
+#define CLK_SRC_TOP2_VAL	((MUX_BPLL_USER_SEL << 24) \
+				| (MUX_MPLL_USER_SEL << 20) \
+				| (MUX_VPLL_SEL << 16) \
+				| (MUX_EPLL_SEL << 12) \
+				| (MUX_CPLL_SEL << 8) \
+				| (VPLLSRC_SEL))
+/* CLK_SRC_TOP3 */
+#define MUX_ACLK_333_SUB_SEL		0x1
+#define MUX_ACLK_400_SUB_SEL		0x1
+#define MUX_ACLK_266_ISP_SUB_SEL	0x1
+#define MUX_ACLK_266_GPS_SUB_SEL	0x1
+#define MUX_ACLK_300_GSCL_SUB_SEL	0x1
+#define MUX_ACLK_266_GSCL_SUB_SEL	0x1
+#define MUX_ACLK_300_DISP1_SUB_SEL	0x1
+#define MUX_ACLK_200_DISP1_SUB_SEL	0x1
+#define CLK_SRC_TOP3_VAL		((MUX_ACLK_333_SUB_SEL << 24) \
+					| (MUX_ACLK_400_SUB_SEL << 20) \
+					| (MUX_ACLK_266_ISP_SUB_SEL << 16) \
+					| (MUX_ACLK_266_GPS_SUB_SEL << 12) \
+					| (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
+					| (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
+					| (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
+					| (MUX_ACLK_200_DISP1_SUB_SEL << 4))
+
+/* CLK_DIV_TOP0 */
+#define ACLK_300_RATIO		0x0
+#define ACLK_400_RATIO		0x3
+#define ACLK_333_RATIO		0x2
+#define ACLK_266_RATIO		0x2
+#define ACLK_200_RATIO		0x3
+#define ACLK_166_RATIO		0x5
+#define ACLK_133_RATIO		0x1
+#define ACLK_66_RATIO		0x5
+#define CLK_DIV_TOP0_VAL	((ACLK_300_RATIO << 28) \
+				| (ACLK_400_RATIO << 24) \
+				| (ACLK_333_RATIO << 20) \
+				| (ACLK_266_RATIO << 16) \
+				| (ACLK_200_RATIO << 12) \
+				| (ACLK_166_RATIO << 8) \
+				| (ACLK_133_RATIO << 4) \
+				| (ACLK_66_RATIO))
+
+/* CLK_DIV_TOP1 */
+#define ACLK_MIPI_HSI_TX_BASE_RATIO	0x3
+#define ACLK_66_PRE_RATIO	0x1
+#define ACLK_400_ISP_RATIO	0x1
+#define ACLK_400_IOP_RATIO	0x1
+#define ACLK_300_GSCL_RATIO	0x0
+#define ACLK_266_GPS_RATIO	0x7
+
+#define CLK_DIV_TOP1_VAL	((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
+				| (ACLK_66_PRE_RATIO << 24) \
+				| (ACLK_400_ISP_RATIO << 20) \
+				| (ACLK_400_IOP_RATIO << 16) \
+				| (ACLK_300_GSCL_RATIO << 12) \
+				| (ACLK_266_GPS_RATIO << 8))
+
+/* APLL_LOCK */
+#define APLL_LOCK_VAL		(0x3E8)
+/* MPLL_LOCK */
+#define MPLL_LOCK_VAL		(0x2F1)
+/* CPLL_LOCK */
+#define CPLL_LOCK_VAL		(0x3E8)
+/* EPLL_LOCK */
+#define EPLL_LOCK_VAL		(0x2321)
+/* VPLL_LOCK */
+#define VPLL_LOCK_VAL		(0x2321)
+/* BPLL_LOCK */
+#define BPLL_LOCK_VAL		(0x3E8)
+
+/* CLK_SRC_PERIC0 */
+/* SRC_CLOCK = SCLK_MPLL */
+#define PWM_SEL			0
+#define UART4_SEL		6
+#define UART3_SEL		6
+#define UART2_SEL		6
+#define UART1_SEL		6
+#define UART0_SEL		6
+#define CLK_SRC_PERIC0_VAL	((PWM_SEL << 24) \
+				| (UART4_SEL << 16) \
+				| (UART3_SEL << 12) \
+				| (UART2_SEL << 8) \
+				| (UART1_SEL << 4) \
+				| (UART0_SEL << 0))
+
+#define CLK_SRC_FSYS_VAL	0x66666
+#define CLK_DIV_FSYS0_VAL	0x0BB00000
+#define CLK_DIV_FSYS1_VAL	0x000f000f
+#define CLK_DIV_FSYS2_VAL	0x020f020f
+#define CLK_DIV_FSYS3_VAL	0x000f
+
+/* CLK_DIV_PERIC0 */
+#define UART5_RATIO		8
+#define UART4_RATIO		8
+#define UART3_RATIO		8
+#define UART2_RATIO		8
+#define UART1_RATIO		8
+#define UART0_RATIO		8
+#define CLK_DIV_PERIC0_VAL	((UART4_RATIO << 16) \
+				| (UART3_RATIO << 12) \
+				| (UART2_RATIO << 8) \
+				| (UART1_RATIO << 4) \
+				| (UART0_RATIO << 0))
+
+/* CLK_DIV_PERIC3 */
+#define PWM_RATIO		8
+#define CLK_DIV_PERIC3_VAL	(PWM_RATIO << 0)
+
+/* CLK_SRC_LEX */
+#define CLK_SRC_LEX_VAL		0x0
+
+/* CLK_DIV_LEX */
+#define CLK_DIV_LEX_VAL		0x10
+
+/* CLK_DIV_R0X */
+#define CLK_DIV_R0X_VAL		0x10
+
+/* CLK_DIV_L0X */
+#define CLK_DIV_R1X_VAL		0x10
+
+/* SCLK_SRC_ISP */
+#define SCLK_SRC_ISP_VAL	0x600
+/* CLK_DIV_ISP0 */
+#define CLK_DIV_ISP0_VAL	0x31
+
+/* CLK_DIV_ISP1 */
+#define CLK_DIV_ISP1_VAL	0x0
+
+/* CLK_DIV_ISP2 */
+#define CLK_DIV_ISP2_VAL	0x1
+
+#define MPLL_DEC	(MPLL_MDIV * MPLL_MDIV / (MPLL_PDIV * 2^(MPLL_SDIV-1)))
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE			0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET		0xFF
+
+/* DMC Init */
+#define SET			1
+#define RESET			0
+/* (Memory Interleaving Size = 1 << IV_SIZE) */
+#define CONFIG_IV_SIZE		0x07
+
+#define PHY_RESET_VAL	(0 << 0)
+
+/*ZQ Configurations */
+#define PHY_CON16_RESET_VAL	0x08000304
+
+#define ZQ_MODE_DDS_VAL		(0x5 << 24)
+#define ZQ_MODE_TERM_VAL	(0x5 << 21)
+#define SET_ZQ_MODE_DDS_VAL(x)	(x = (x & ~(0x7 << 24)) | ZQ_MODE_DDS_VAL)
+#define SET_ZQ_MODE_TERM_VAL(x)	(x = (x & ~(0x7 << 21)) | ZQ_MODE_TERM_VAL)
+
+#define ZQ_MODE_NOTERM		(1 << 19)
+#define ZQ_CLK_DIV_EN		(1 << 18)
+#define ZQ_MANUAL_STR		(1 << 1)
+
+/* Channel and Chip Selection */
+#define CONFIG_DMC_CHANNELS		2
+#define CONFIG_CHIPS_PER_CHANNEL	2
+
+#define SET_CMD_CHANNEL(x, y)	(x = (x & ~(1 << 28)) | y << 28)
+#define SET_CMD_CHIP(x, y)	(x = (x & ~(1 << 20)) | y << 20)
+
+/* Diret Command */
+#define	DIRECT_CMD_NOP		0x07000000
+#define DIRECT_CMD_MRS1		0x00071C00
+#define DIRECT_CMD_MRS2		0x00010BFC
+#define DIRECT_CMD_MRS3		0x00000708
+#define DIRECT_CMD_MRS4		0x00000818
+#define	DIRECT_CMD_PALL		0x01000000
+
+/* DLL Resync */
+#define FP_RSYNC		(1 << 3)
+
+#define CONFIG_CTRL_DLL_ON(x, y)	(x = (x & ~(1 << 5)) | y << 5)
+#define CONFIG_CTRL_START(x, y)		(x = (x & ~(1 << 6)) | y << 6)
+#define SET_CTRL_FORCE_VAL(x, y)	(x = (x & ~(0x7F << 8)) | y << 8)
+
+/* RDLVL */
+#define PHY_CON0_RESET_VAL	0x17023240
+#define DDR_MODE_LPDDR2		0x2
+#define BYTE_RDLVL_EN		(1 << 13)
+#define CTRL_ATGATE		(1 << 6)
+#define SET_CTRL_DDR_MODE(x, y)	(x = (x & ~(0x3 << 11)) | y << 11)
+
+#define PHY_CON1_RESET_VAL	0x9210100
+#define RDLVL_RDDATAPADJ	0x1
+#define SET_RDLVL_RDDATAPADJ	((PHY_CON1_RESET_VAL & ~(0xFFFF << 0))\
+					| RDLVL_RDDATAPADJ << 0)
+
+#define PHY_CON2_RESET_VAL	0x00010004
+#define RDLVL_EN		(1 << 25)
+#define RDDSKEW_CLEAR		(1 << 13)
+
+#define CTRL_RDLVL_DATA_EN	(1 << 1)
+#define LPDDR2_ADDR		0x00000208
+
+#define DMC_MEMCONFIG0_VAL	0x00001323
+#define DMC_MEMCONFIG1_VAL	0x00001323
+#define DMC_MEMBASECONFIG0_VAL	0x00400780
+#define DMC_MEMBASECONFIG1_VAL	0x00800780
+#define DMC_MEMCONTROL_VAL	0x00212500
+#define DMC_PRECHCONFIG_VAL		0xFF000000
+#define DMC_PWRDNCONFIG_VAL		0xFFFF00FF
+#define DMC_TIMINGREF_VAL		0x0000005D
+#define DMC_TIMINGROW_VAL		0x2336544C
+#define DMC_TIMINGDATA_VAL		0x24202408
+#define DMC_TIMINGPOWER_VAL		0x38260235
+
+#define CTRL_BSTLEN		0x04
+#define CTRL_RDLAT		0x08
+#define PHY_CON42_VAL		(CTRL_BSTLEN << 8 | CTRL_RDLAT << 0)
+
+/* DQS, DQ, DEBUG offsets */
+#define	SET_DQS_OFFSET_VAL	0x7F7F7F7F
+#define	SET_DQ_OFFSET_VAL	0x7F7F7F7F
+#define	SET_DEBUG_OFFSET_VAL	0x7F
+
+#define	RESET_DQS_OFFSET_VAL	0x08080808
+#define	RESET_DQ_OFFSET_VAL	0x08080808
+#define	RESET_DEBUG_OFFSET_VAL	0x8
+
+#define CTRL_PULLD_DQ		(0x0F << 8)
+#define CTRL_PULLD_DQS		(0x0F << 0)
+
+#define DFI_INIT_START		(1 << 28)
+
+#define CLK_STOP_EN	(1 << 0)
+#define DPWRDN_EN	(1 << 1)
+#define DSREF_EN	(1 << 5)
+
+#define AREF_EN			(1 << 5)
+void sdelay(unsigned long);
+void mem_ctrl_init(void);
+void system_clock_init(void);
+void tzpc_init(void);
+
+#endif
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c
new file mode 100644
index 0000000..04c863a
--- /dev/null
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/sromc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+struct exynos5_gpio_part1 *gpio1;
+
+int board_init(void)
+{
+	gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+
+	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size	= get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
+							PHYS_SDRAM_1_SIZE);
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
+							PHYS_SDRAM_2_SIZE);
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
+							PHYS_SDRAM_3_SIZE);
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
+							PHYS_SDRAM_4_SIZE);
+	gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
+	gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5,
+							PHYS_SDRAM_5_SIZE);
+	gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
+	gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6,
+							PHYS_SDRAM_6_SIZE);
+	gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
+	gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7,
+							PHYS_SDRAM_7_SIZE);
+	gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
+	gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8,
+							PHYS_SDRAM_8_SIZE);
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	printf("\nBoard: SMDK5250\n");
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	int i, err;
+
+	/*
+	 * MMC2 SD card GPIO:
+	 *
+	 * GPC2[0]	SD_2_CLK(2)
+	 * GPC2[1]	SD_2_CMD(2)
+	 * GPC2[2]	SD_2_CDn
+	 * GPC2[3:6]	SD_2_DATA[0:3](2)
+	 */
+	for (i = 0; i < 7; i++) {
+		/* GPC2[0:6] special function 2 */
+		s5p_gpio_cfg_pin(&gpio1->c2, i, GPIO_FUNC(0x2));
+
+		/* GPK2[0:6] drv 4x */
+		s5p_gpio_set_drv(&gpio1->c2, i, GPIO_DRV_4X);
+
+		/* GPK2[0:1] pull disable */
+		if (i == 0 || i == 1) {
+			s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_NONE);
+			continue;
+		}
+
+		/* GPK2[2:6] pull up */
+		s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_UP);
+	}
+
+	err = s5p_mmc_init(2, 4);
+	return err;
+}
+#endif
+
+static void board_uart_init(void)
+{
+	struct exynos5_gpio_part1 *gpio1 =
+		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+	int i;
+
+	/* UART1 GPIOs (part1) : GPA0CON[7:4] 0x2222 */
+	for (i = 4; i < 8; i++) {
+		s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE);
+		s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2));
+	}
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	board_uart_init();
+	return 0;
+}
+#endif
diff --git a/board/samsung/smdk5250/tzpc_init.c b/board/samsung/smdk5250/tzpc_init.c
new file mode 100644
index 0000000..c2ccef3
--- /dev/null
+++ b/board/samsung/smdk5250/tzpc_init.c
@@ -0,0 +1,48 @@
+/*
+ * Lowlevel setup for SMDK5250 board based on S5PC520
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/tzpc.h>
+#include"setup.h"
+
+/* Setting TZPC[TrustZone Protection Controller] */
+void tzpc_init(void)
+{
+	struct exynos5_tzpc *tzpc;
+	unsigned int addr;
+
+	for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) {
+		tzpc = (struct exynos5_tzpc *)addr;
+
+		if (addr == TZPC0_BASE)
+			writel(R0SIZE, &tzpc->r0size);
+
+		writel(DECPROTXSET, &tzpc->decprot0set);
+		writel(DECPROTXSET, &tzpc->decprot1set);
+
+		if (addr != TZPC9_BASE) {
+			writel(DECPROTXSET, &tzpc->decprot2set);
+			writel(DECPROTXSET, &tzpc->decprot3set);
+		}
+	}
+}