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author | Rajeshwari Shinde <rajeshwari.s@samsung.com> | 2012-07-03 20:02:56 +0000 |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:23 +0200 |
commit | 87f2e079dbbe517003bd2c3910ae2512ab27a6f5 (patch) | |
tree | 0fd32aed7950df0e9080e746e300a8e8ed44511b /board/samsung/smdk5250/setup.h | |
parent | 998e5d393f335de92fbde81c804c88be4b833cf7 (diff) | |
download | u-boot-imx-87f2e079dbbe517003bd2c3910ae2512ab27a6f5.zip u-boot-imx-87f2e079dbbe517003bd2c3910ae2512ab27a6f5.tar.gz u-boot-imx-87f2e079dbbe517003bd2c3910ae2512ab27a6f5.tar.bz2 |
Exynos5: DDR3: Add DDR3 memory setup for Exynos5250 Rev 1.0
The patch adds the memory initialization sequence of DDR3.
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'board/samsung/smdk5250/setup.h')
-rw-r--r-- | board/samsung/smdk5250/setup.h | 59 |
1 files changed, 58 insertions, 1 deletions
diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h index 4bdd095..a159601 100644 --- a/board/samsung/smdk5250/setup.h +++ b/board/samsung/smdk5250/setup.h @@ -529,9 +529,66 @@ enum { SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2, }; +/* + * Memory variant specific initialization code + * + * @param mem Memory timings for this memory type. + * @param mem_iv_size Memory interleaving size is a configurable parameter + * which the DMC uses to decide how to split a memory + * chunk into smaller chunks to support concurrent + * accesses; may vary across boards. + * @return 0 if ok, SETUP_ERR_... if there is a problem + */ +int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size); + +/* + * Configure ZQ I/O interface + * + * @param mem Memory timings for this memory type. + * @param phy0_ctrl Pointer to struct containing PHY0 control reg + * @param phy1_ctrl Pointer to struct containing PHY1 control reg + * @return 0 if ok, -1 on error + */ +int dmc_config_zq(struct mem_timings *mem, + struct exynos5_phy_control *phy0_ctrl, + struct exynos5_phy_control *phy1_ctrl); + +/* + * Send NOP and MRS/EMRS Direct commands + * + * @param mem Memory timings for this memory type. + * @param dmc Pointer to struct of DMC registers + */ +void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc); + +/* + * Send PALL Direct commands + * + * @param mem Memory timings for this memory type. + * @param dmc Pointer to struct of DMC registers + */ +void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc); + +/* + * Configure the memconfig and membaseconfig registers + * + * @param mem Memory timings for this memory type. + * @param exynos5_dmc Pointer to struct of DMC registers + */ +void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc); + +/* + * Reset the DLL. This function is common between DDR3 and LPDDR2. + * However, the reset value is different. So we are passing a flag + * ddr_mode to distinguish between LPDDR2 and DDR3. + * + * @param exynos5_dmc Pointer to struct of DMC registers + * @param ddr_mode Type of DDR memory + */ +void update_reset_dll(struct exynos5_dmc *, enum ddr_mode); + void sdelay(unsigned long); void mem_ctrl_init(void); void system_clock_init(void); void tzpc_init(void); - #endif |