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| author | Inderpal Singh <inderpal.singh@linaro.org> | 2013-04-04 23:09:19 +0000 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2013-06-04 15:22:10 +0900 |
| commit | 72af2fc8504daccd2f8ae2459e3e225e9c2cc512 (patch) | |
| tree | ea03f1116b36b7661be4c9552607f159dfae9ed0 /board/samsung/smdk5250/setup.h | |
| parent | ffbff1dd6e6a25cc7db60576ad64e7bd570fa643 (diff) | |
| download | u-boot-imx-72af2fc8504daccd2f8ae2459e3e225e9c2cc512.zip u-boot-imx-72af2fc8504daccd2f8ae2459e3e225e9c2cc512.tar.gz u-boot-imx-72af2fc8504daccd2f8ae2459e3e225e9c2cc512.tar.bz2 | |
exynos: move tzpc_init to armv7/exynos
tzpc_init is common for all exynos5 boards, hence move it to
armv7/exynos so that all other boards can use it.
Also update the smdk5250 Makefile and config file.
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'board/samsung/smdk5250/setup.h')
| -rw-r--r-- | board/samsung/smdk5250/setup.h | 25 |
1 files changed, 0 insertions, 25 deletions
diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h index 34d8bc31..eb91d13 100644 --- a/board/samsung/smdk5250/setup.h +++ b/board/samsung/smdk5250/setup.h @@ -28,18 +28,6 @@ #include <config.h> #include <asm/arch/dmc.h> -/* TZPC : Register Offsets */ -#define TZPC0_BASE 0x10100000 -#define TZPC1_BASE 0x10110000 -#define TZPC2_BASE 0x10120000 -#define TZPC3_BASE 0x10130000 -#define TZPC4_BASE 0x10140000 -#define TZPC5_BASE 0x10150000 -#define TZPC6_BASE 0x10160000 -#define TZPC7_BASE 0x10170000 -#define TZPC8_BASE 0x10180000 -#define TZPC9_BASE 0x10190000 - /* APLL_CON1 */ #define APLL_CON1_VAL (0x00203800) @@ -458,18 +446,6 @@ /* CLK_GATE_IP_DISP1 */ #define CLK_GATE_DP1_ALLOW (1 << 4) -/* - * TZPC Register Value : - * R0SIZE: 0x0 : Size of secured ram - */ -#define R0SIZE 0x0 - -/* - * TZPC Decode Protection Register Value : - * DECPROTXSET: 0xFF : Set Decode region to non-secure - */ -#define DECPROTXSET 0xFF - #define DDR3PHY_CTRL_PHY_RESET (1 << 0) #define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0) @@ -590,5 +566,4 @@ void update_reset_dll(struct exynos5_dmc *, enum ddr_mode); void sdelay(unsigned long); void mem_ctrl_init(void); void system_clock_init(void); -void tzpc_init(void); #endif |