EXYNOS: Move files from board/samsung to arch/arm

This patch performs the following:

1) Convert the assembly code for memory and clock initialization to C code.
2) Move the memory and clock init codes from board/samsung to arch/arm
3) Creat a common lowlevel_init file across Exynos4 and Exynos5. Converted
   the common lowlevel_init from assembly to C-code
4) Made spl_boot.c and tzpc_init.c common for both exynos4 and exynos5.
5) Enable CONFIG_SKIP_LOWLEVEL_INIT as stack pointer initialisation is already
   done in _main.
6) exynos-uboot-spl.lds made common across SMDKV310, Origen and SMDK5250.

TEST: Tested SD-MMC boot on SMDK5250 and Origen.
      Tested USB and SPI boot on SMDK5250
      Compile tested for SMDKV310.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

5 files changed, 2 insertions, 1452 deletions

diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile
index 3a885a5..63c8b46 100644
--- a/board/samsung/origen/Makefile
+++ b/board/samsung/origen/Makefile
@@ -24,19 +24,12 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-SOBJS	:= mem_setup.o
-SOBJS	+= lowlevel_init.o
-
 ifndef CONFIG_SPL_BUILD
 COBJS	+= origen.o
 endif
 
-ifdef CONFIG_SPL_BUILD
-COBJS	+= mmc_boot.o
-endif
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 ALL	+=$(obj).depend $(LIB)
 
diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S
deleted file mode 100644
index be9d418..0000000
--- a/board/samsung/origen/lowlevel_init.S
+++ /dev/null
@@ -1,357 +0,0 @@
-/*
- * Lowlevel setup for ORIGEN board based on EXYNOS4210
- *
- * Copyright (C) 2011 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-#include "origen_setup.h"
-/*
- * Register usages:
- *
- * r5 has zero always
- * r7 has GPIO part1 base 0x11400000
- * r6 has GPIO part2 base 0x11000000
- */
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-	.globl lowlevel_init
-lowlevel_init:
-	push	{lr}
-
-	/* r5 has always zero */
-	mov	r5, #0
-	ldr	r7, =EXYNOS4_GPIO_PART1_BASE
-	ldr	r6, =EXYNOS4_GPIO_PART2_BASE
-
-	/* check reset status */
-	ldr	r0, =(EXYNOS4_POWER_BASE + INFORM1_OFFSET)
-	ldr	r1, [r0]
-
-	/* AFTR wakeup reset */
-	ldr	r2, =S5P_CHECK_DIDLE
-	cmp	r1, r2
-	beq	exit_wakeup
-
-	/* LPA wakeup reset */
-	ldr	r2, =S5P_CHECK_LPA
-	cmp	r1, r2
-	beq	exit_wakeup
-
-	/* Sleep wakeup reset */
-	ldr	r2, =S5P_CHECK_SLEEP
-	cmp	r1, r2
-	beq	wakeup_reset
-
-	/*
-	 * If U-boot is already running in ram, no need to relocate U-Boot.
-	 * Memory controller must be configured before relocating U-Boot
-	 * in ram.
-	 */
-	ldr	r0, =0x0ffffff		/* r0 <- Mask Bits*/
-	bic	r1, pc, r0		/* pc <- current addr of code */
-					/* r1 <- unmasked bits of pc */
-	ldr	r2, _TEXT_BASE		/* r2 <- original base addr in ram */
-	bic	r2, r2, r0		/* r2 <- unmasked bits of r2*/
-	cmp	r1, r2			/* compare r1, r2 */
-	beq	1f			/* r0 == r1 then skip sdram init */
-
-	/* init system clock */
-	bl system_clock_init
-
-	/* Memory initialize */
-	bl mem_ctrl_asm_init
-
-1:
-	/* for UART */
-	bl uart_asm_init
-	bl arch_cpu_init
-	bl tzpc_init
-	pop	{pc}
-
-wakeup_reset:
-	bl system_clock_init
-	bl mem_ctrl_asm_init
-	bl arch_cpu_init
-	bl tzpc_init
-
-exit_wakeup:
-	/* Load return address and jump to kernel */
-	ldr	r0, =(EXYNOS4_POWER_BASE + INFORM0_OFFSET)
-
-	/* r1 = physical address of exynos4210_cpu_resume function */
-	ldr	r1, [r0]
-
-	/* Jump to kernel*/
-	mov	pc, r1
-	nop
-	nop
-
-/*
- * system_clock_init: Initialize core clock and bus clock.
- * void system_clock_init(void)
- */
-system_clock_init:
-	push	{lr}
-	ldr	r0, =EXYNOS4_CLOCK_BASE
-
-	/* APLL(1), MPLL(1), CORE(0), HPM(0) */
-	ldr	r1, =CLK_SRC_CPU_VAL
-	ldr	r2, =CLK_SRC_CPU_OFFSET
-	str	r1, [r0, r2]
-
-	/* wait ?us */
-	mov	r1, #0x10000
-2:	subs	r1, r1, #1
-	bne	2b
-
-	ldr	r1, =CLK_SRC_TOP0_VAL
-	ldr	r2, =CLK_SRC_TOP0_OFFSET
-	str	r1, [r0, r2]
-
-	ldr	r1, =CLK_SRC_TOP1_VAL
-	ldr	r2, =CLK_SRC_TOP1_OFFSET
-	str	r1, [r0, r2]
-
-	/* DMC */
-	ldr	r1, =CLK_SRC_DMC_VAL
-	ldr	r2, =CLK_SRC_DMC_OFFSET
-	str	r1, [r0, r2]
-
-	/*CLK_SRC_LEFTBUS */
-	ldr	r1, =CLK_SRC_LEFTBUS_VAL
-	ldr	r2, =CLK_SRC_LEFTBUS_OFFSET
-	str	r1, [r0, r2]
-
-	/*CLK_SRC_RIGHTBUS */
-	ldr	r1, =CLK_SRC_RIGHTBUS_VAL
-	ldr	r2, =CLK_SRC_RIGHTBUS_OFFSET
-	str	r1, [r0, r2]
-
-	/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
-	ldr	r1, =CLK_SRC_FSYS_VAL
-	ldr	r2, =CLK_SRC_FSYS_OFFSET
-	str	r1, [r0, r2]
-
-	/* UART[0:4] */
-	ldr	r1, =CLK_SRC_PERIL0_VAL
-	ldr	r2, =CLK_SRC_PERIL0_OFFSET
-	str	r1, [r0, r2]
-
-	/* CAM , FIMC 0-3 */
-	ldr	r1, =CLK_SRC_CAM_VAL
-	ldr	r2, =CLK_SRC_CAM_OFFSET
-	str	r1, [r0, r2]
-
-	/* MFC */
-	ldr	r1, =CLK_SRC_MFC_VAL
-	ldr	r2, =CLK_SRC_MFC_OFFSET
-	str	r1, [r0, r2]
-
-	/* G3D */
-	ldr	r1, =CLK_SRC_G3D_VAL
-	ldr	r2, =CLK_SRC_G3D_OFFSET
-	str	r1, [r0, r2]
-
-	/* LCD0 */
-	ldr	r1, =CLK_SRC_LCD0_VAL
-	ldr	r2, =CLK_SRC_LCD0_OFFSET
-	str	r1, [r0, r2]
-
-	/* wait ?us */
-	mov	r1, #0x10000
-3:	subs	r1, r1, #1
-	bne	3b
-
-	/* CLK_DIV_CPU0 */
-	ldr	r1, =CLK_DIV_CPU0_VAL
-	ldr	r2, =CLK_DIV_CPU0_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_CPU1 */
-	ldr	r1, =CLK_DIV_CPU1_VAL
-	ldr	r2, =CLK_DIV_CPU1_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_DMC0 */
-	ldr	r1, =CLK_DIV_DMC0_VAL
-	ldr	r2, =CLK_DIV_DMC0_OFFSET
-	str	r1, [r0, r2]
-
-	/*CLK_DIV_DMC1 */
-	ldr	r1, =CLK_DIV_DMC1_VAL
-	ldr	r2, =CLK_DIV_DMC1_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_LEFTBUS */
-	ldr	r1, =CLK_DIV_LEFTBUS_VAL
-	ldr	r2, =CLK_DIV_LEFTBUS_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_RIGHTBUS */
-	ldr	r1, =CLK_DIV_RIGHTBUS_VAL
-	ldr	r2, =CLK_DIV_RIGHTBUS_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_TOP */
-	ldr	r1, =CLK_DIV_TOP_VAL
-	ldr	r2, =CLK_DIV_TOP_OFFSET
-	str	r1, [r0, r2]
-
-	/* MMC[0:1] */
-	ldr	r1, =CLK_DIV_FSYS1_VAL		/* 800(MPLL) / (15 + 1) */
-	ldr	r2, =CLK_DIV_FSYS1_OFFSET
-	str	r1, [r0, r2]
-
-	/* MMC[2:3] */
-	ldr	r1, =CLK_DIV_FSYS2_VAL		/* 800(MPLL) / (15 + 1) */
-	ldr	r2, =CLK_DIV_FSYS2_OFFSET
-	str	r1, [r0, r2]
-
-	/* MMC4 */
-	ldr	r1, =CLK_DIV_FSYS3_VAL		/* 800(MPLL) / (15 + 1) */
-	ldr	r2, =CLK_DIV_FSYS3_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_PERIL0: UART Clock Divisors */
-	ldr	r1, =CLK_DIV_PERIL0_VAL
-	ldr	r2, =CLK_DIV_PERIL0_OFFSET
-	str	r1, [r0, r2]
-
-	/* CAM, FIMC 0-3: CAM Clock Divisors */
-	ldr	r1, =CLK_DIV_CAM_VAL
-	ldr	r2, =CLK_DIV_CAM_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_MFC: MFC Clock Divisors */
-	ldr	r1, =CLK_DIV_MFC_VAL
-	ldr	r2, =CLK_DIV_MFC_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_G3D: G3D Clock Divisors */
-	ldr	r1, =CLK_DIV_G3D_VAL
-	ldr	r2, =CLK_DIV_G3D_OFFSET
-	str	r1, [r0, r2]
-
-	/* CLK_DIV_LCD0: LCD0 Clock Divisors */
-	ldr	r1, =CLK_DIV_LCD0_VAL
-	ldr	r2, =CLK_DIV_LCD0_OFFSET
-	str	r1, [r0, r2]
-
-	/* Set PLL locktime */
-	ldr	r1, =PLL_LOCKTIME
-	ldr	r2, =APLL_LOCK_OFFSET
-	str	r1, [r0, r2]
-
-	ldr	r1, =PLL_LOCKTIME
-	ldr	r2, =MPLL_LOCK_OFFSET
-	str	r1, [r0, r2]
-
-	ldr	r1, =PLL_LOCKTIME
-	ldr	r2, =EPLL_LOCK_OFFSET
-	str	r1, [r0, r2]
-
-	ldr	r1, =PLL_LOCKTIME
-	ldr	r2, =VPLL_LOCK_OFFSET
-	str	r1, [r0, r2]
-
-	/* APLL_CON1 */
-	ldr	r1, =APLL_CON1_VAL
-	ldr	r2, =APLL_CON1_OFFSET
-	str	r1, [r0, r2]
-
-	/* APLL_CON0 */
-	ldr	r1, =APLL_CON0_VAL
-	ldr	r2, =APLL_CON0_OFFSET
-	str	r1, [r0, r2]
-
-	/* MPLL_CON1 */
-	ldr	r1, =MPLL_CON1_VAL
-	ldr	r2, =MPLL_CON1_OFFSET
-	str	r1, [r0, r2]
-
-	/* MPLL_CON0 */
-	ldr	r1, =MPLL_CON0_VAL
-	ldr	r2, =MPLL_CON0_OFFSET
-	str	r1, [r0, r2]
-
-	/* EPLL */
-	ldr	r1, =EPLL_CON1_VAL
-	ldr	r2, =EPLL_CON1_OFFSET
-	str	r1, [r0, r2]
-
-	/* EPLL_CON0 */
-	ldr	r1, =EPLL_CON0_VAL
-	ldr	r2, =EPLL_CON0_OFFSET
-	str	r1, [r0, r2]
-
-	/* VPLL_CON1 */
-	ldr	r1, =VPLL_CON1_VAL
-	ldr	r2, =VPLL_CON1_OFFSET
-	str	r1, [r0, r2]
-
-	/* VPLL_CON0 */
-	ldr	r1, =VPLL_CON0_VAL
-	ldr	r2, =VPLL_CON0_OFFSET
-	str	r1, [r0, r2]
-
-	/* wait ?us */
-	mov	r1, #0x30000
-4:	subs	r1, r1, #1
-	bne	4b
-
-	pop	{pc}
-/*
- * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
- * void uart_asm_init(void)
- */
-	.globl uart_asm_init
-uart_asm_init:
-
-	/* setup UART0-UART3 GPIOs (part1) */
-	mov	r0, r7
-	ldr	r1, =EXYNOS4_GPIO_A0_CON_VAL
-	str	r1, [r0, #EXYNOS4_GPIO_A0_CON_OFFSET]
-	ldr	r1, =EXYNOS4_GPIO_A1_CON_VAL
-	str	r1, [r0, #EXYNOS4_GPIO_A1_CON_OFFSET]
-
-	ldr r0, =EXYNOS4_UART_BASE
-	add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
-
-	ldr	r1, =ULCON_VAL
-	str	r1, [r0, #ULCON_OFFSET]
-	ldr	r1, =UCON_VAL
-	str	r1, [r0, #UCON_OFFSET]
-	ldr	r1, =UFCON_VAL
-	str	r1, [r0, #UFCON_OFFSET]
-	ldr	r1, =UBRDIV_VAL
-	str	r1, [r0, #UBRDIV_OFFSET]
-	ldr	r1, =UFRACVAL_VAL
-	str	r1, [r0, #UFRACVAL_OFFSET]
-	mov	pc, lr
-	nop
-	nop
-	nop
-
diff --git a/board/samsung/origen/mem_setup.S b/board/samsung/origen/mem_setup.S
deleted file mode 100644
index b49b193..0000000
--- a/board/samsung/origen/mem_setup.S
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * Memory setup for ORIGEN board based on EXYNOS4210
- *
- * Copyright (C) 2011 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include "origen_setup.h"
-#define SET_MIU
-
-	.globl mem_ctrl_asm_init
-mem_ctrl_asm_init:
-	/*
-	 * Async bridge configuration at CPU_core:
-	 * 1: half_sync
-	 * 0: full_sync
-	 */
-	ldr r0, =ASYNC_CONFIG
-	mov r1, #1
-	str r1, [r0]
-
-#ifdef SET_MIU
-	ldr	r0, =EXYNOS4_MIU_BASE
-	/* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */
-	ldr	r1, =0x20001507
-	str	r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET]
-
-	/* Update MIU Configuration */
-	ldr	r1, =0x00000001
-	str	r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET]
-#endif
-	/* DREX0 */
-	ldr	r0, =EXYNOS4_DMC0_BASE
-
-	/*
-	 * DLL Parameter Setting:
-	 * Termination: Enable R/W
-	 * Phase Delay for DQS Cleaning: 180' Shift
-	 */
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/*
-	 * ZQ Calibration
-	 * Termination: Disable
-	 * Auto Calibration Start: Enable
-	 */
-	ldr	r1, =0xE3855703
-	str	r1, [r0, #DMC_PHYZQCONTROL]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-1:	subs	r2, r2, #1
-	bne	1b
-
-	/*
-	 * Update DLL Information:
-	 * Force DLL Resyncronization
-	 */
-	ldr	r1, =0xe000008e
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/* Reset Force DLL Resyncronization */
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/* Enable Differential DQS, DLL Off*/
-	ldr	r1, =0x71101008
-	str	r1, [r0, #DMC_PHYCONTROL0]
-
-	/* Activate PHY DLL: DLL On */
-	ldr	r1, =0x7110100A
-	str	r1, [r0, #DMC_PHYCONTROL0]
-
-	/* Set DLL Parameters */
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/* DLL Start */
-	ldr	r1, =0x7110100B
-	str	r1, [r0, #DMC_PHYCONTROL0]
-
-	ldr	r1, =0x00000000
-	str	r1, [r0, #DMC_PHYCONTROL2]
-
-	/* Set Clock Ratio of Bus clock to Memory Clock */
-	ldr	r1, =0x0FFF301a
-	str	r1, [r0, #DMC_CONCONTROL]
-
-	/*
-	 * Memor Burst length: 8
-	 * Number of chips: 2
-	 * Memory Bus width: 32 bit
-	 * Memory Type: DDR3
-	 * Additional Latancy for PLL: 1 Cycle
-	 */
-	ldr	r1, =0x00312640
-	str	r1, [r0, #DMC_MEMCONTROL]
-
-	/*
-	 * Memory Configuration Chip 0
-	 * Address Mapping: Interleaved
-	 * Number of Column address Bits: 10 bits
-	 * Number of Rows Address Bits: 14
-	 * Number of Banks: 8
-	 */
-	ldr	r1, =0x20e01323
-	str	r1, [r0, #DMC_MEMCONFIG0]
-
-	/*
-	 * Memory Configuration Chip 1
-	 * Address Mapping: Interleaved
-	 * Number of Column address Bits: 10 bits
-	 * Number of Rows Address Bits: 14
-	 * Number of Banks: 8
-	 */
-	ldr	r1, =0x40e01323
-	str	r1, [r0, #DMC_MEMCONFIG1]
-
-	/* Config Precharge Policy */
-	ldr	r1, =0xff000000
-	str	r1, [r0, #DMC_PRECHCONFIG]
-
-	/*
-	 * TimingAref, TimingRow, TimingData, TimingPower Setting:
-	 * Values as per Memory AC Parameters
-	 */
-	ldr	r1, =0x000000BB
-	str	r1, [r0, #DMC_TIMINGAREF]
-	ldr	r1, =0x4046654f
-	str	r1, [r0, #DMC_TIMINGROW]
-	ldr	r1, =0x46400506
-	str	r1, [r0, #DMC_TIMINGDATA]
-	ldr	r1, =0x52000A3C
-	str	r1, [r0, #DMC_TIMINGPOWER]
-
-	/* Chip0: NOP Command: Assert and Hold CKE to high level */
-	ldr	r1, =0x07000000
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-2:	subs	r2, r2, #1
-	bne	2b
-
-	/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
-	ldr	r1, =0x00020000
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00030000
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00010002
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00000328
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-3:	subs	r2, r2, #1
-	bne	3b
-
-	/* Chip0: ZQINIT */
-	ldr	r1, =0x0a000000
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-4:	subs	r2, r2, #1
-	bne	4b
-
-	/* Chip1: NOP Command: Assert and Hold CKE to high level */
-	ldr	r1, =0x07100000
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-5:	subs	r2, r2, #1
-	bne	5b
-
-	/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
-	ldr	r1, =0x00120000
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00130000
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00110002
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00100328
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-6:	subs	r2, r2, #1
-	bne	6b
-
-	/* Chip1: ZQINIT */
-	ldr	r1, =0x0a100000
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-7:	subs	r2, r2, #1
-	bne	7b
-
-	ldr	r1, =0xe000008e
-	str	r1, [r0, #DMC_PHYCONTROL1]
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-8:	subs	r2, r2, #1
-	bne	8b
-
-	/* DREX1 */
-	ldr	r0, =EXYNOS4_DMC1_BASE	@0x10410000
-
-	/*
-	 * DLL Parameter Setting:
-	 * Termination: Enable R/W
-	 * Phase Delay for DQS Cleaning: 180' Shift
-	 */
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/*
-	 * ZQ Calibration:
-	 * Termination: Disable
-	 * Auto Calibration Start: Enable
-	 */
-	ldr	r1, =0xE3855703
-	str	r1, [r0, #DMC_PHYZQCONTROL]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-1:	subs	r2, r2, #1
-	bne	1b
-
-	/*
-	 * Update DLL Information:
-	 * Force DLL Resyncronization
-	 */
-	ldr	r1, =0xe000008e
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/* Reset Force DLL Resyncronization */
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/* Enable Differential DQS, DLL Off*/
-	ldr	r1, =0x71101008
-	str	r1, [r0, #DMC_PHYCONTROL0]
-
-	/* Activate PHY DLL: DLL On */
-	ldr	r1, =0x7110100A
-	str	r1, [r0, #DMC_PHYCONTROL0]
-
-	/* Set DLL Parameters */
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/* DLL Start */
-	ldr	r1, =0x7110100B
-	str	r1, [r0, #DMC_PHYCONTROL0]
-
-	ldr	r1, =0x00000000
-	str	r1, [r0, #DMC_PHYCONTROL2]
-
-	/* Set Clock Ratio of Bus clock to Memory Clock */
-	ldr	r1, =0x0FFF301a
-	str	r1, [r0, #DMC_CONCONTROL]
-
-	/*
-	 * Memor Burst length: 8
-	 * Number of chips: 2
-	 * Memory Bus width: 32 bit
-	 * Memory Type: DDR3
-	 * Additional Latancy for PLL: 1 Cycle
-	 */
-	ldr	r1, =0x00312640
-	str	r1, [r0, #DMC_MEMCONTROL]
-
-	/*
-	 * Memory Configuration Chip 0
-	 * Address Mapping: Interleaved
-	 * Number of Column address Bits: 10 bits
-	 * Number of Rows Address Bits: 14
-	 * Number of Banks: 8
-	 */
-	ldr	r1, =0x20e01323
-	str	r1, [r0, #DMC_MEMCONFIG0]
-
-	/*
-	 * Memory Configuration Chip 1
-	 * Address Mapping: Interleaved
-	 * Number of Column address Bits: 10 bits
-	 * Number of Rows Address Bits: 14
-	 * Number of Banks: 8
-	 */
-	ldr	r1, =0x40e01323
-	str	r1, [r0, #DMC_MEMCONFIG1]
-
-	/* Config Precharge Policy */
-	ldr	r1, =0xff000000
-	str	r1, [r0, #DMC_PRECHCONFIG]
-
-	/*
-	 * TimingAref, TimingRow, TimingData, TimingPower Setting:
-	 * Values as per Memory AC Parameters
-	 */
-	ldr	r1, =0x000000BB
-	str	r1, [r0, #DMC_TIMINGAREF]
-	ldr	r1, =0x4046654f
-	str	r1, [r0, #DMC_TIMINGROW]
-	ldr	r1, =0x46400506
-	str	r1, [r0, #DMC_TIMINGDATA]
-	ldr	r1, =0x52000A3C
-	str	r1, [r0, #DMC_TIMINGPOWER]
-
-	/* Chip0: NOP Command: Assert and Hold CKE to high level */
-	ldr	r1, =0x07000000
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-2:	subs	r2, r2, #1
-	bne	2b
-
-	/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
-	ldr	r1, =0x00020000
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00030000
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00010002
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00000328
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-3:	subs	r2, r2, #1
-	bne	3b
-
-	/* Chip 0: ZQINIT */
-	ldr	r1, =0x0a000000
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-4:	subs	r2, r2, #1
-	bne	4b
-
-	/* Chip1: NOP Command: Assert and Hold CKE to high level */
-	ldr	r1, =0x07100000
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-5:	subs	r2, r2, #1
-	bne	5b
-
-	/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
-	ldr	r1, =0x00120000
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00130000
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00110002
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00100328
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-6:	subs	r2, r2, #1
-	bne	6b
-
-	/* Chip1: ZQINIT */
-	ldr	r1, =0x0a100000
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-7:	subs	r2, r2, #1
-	bne	7b
-
-	ldr	r1, =0xe000008e
-	str	r1, [r0, #DMC_PHYCONTROL1]
-	ldr	r1, =0xe0000086
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	/* Wait ?us*/
-	mov	r2, #0x100000
-8:	subs	r2, r2, #1
-	bne	8b
-
-	/* turn on DREX0, DREX1 */
-	ldr	r0, =EXYNOS4_DMC0_BASE
-	ldr	r1, =0x0FFF303a
-	str	r1, [r0, #DMC_CONCONTROL]
-
-	ldr	r0, =EXYNOS4_DMC1_BASE
-	ldr	r1, =0x0FFF303a
-	str	r1, [r0, #DMC_CONCONTROL]
-
-	mov	pc, lr
diff --git a/board/samsung/origen/mmc_boot.c b/board/samsung/origen/mmc_boot.c
deleted file mode 100644
index 072f161..0000000
--- a/board/samsung/origen/mmc_boot.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include<common.h>
-#include<config.h>
-
-/*
-* Copy U-boot from mmc to RAM:
-* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
-* Pointer to API (Data transfer from mmc to ram)
-*/
-void copy_uboot_to_ram(void)
-{
-	u32 (*copy_bl2)(u32, u32, u32)  = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
-
-	copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
-}
-
-void board_init_f(unsigned long bootflag)
-{
-	__attribute__((noreturn)) void (*uboot)(void);
-	copy_uboot_to_ram();
-
-	/* Jump to U-Boot image */
-	uboot = (void *)CONFIG_SYS_TEXT_BASE;
-	(*uboot)();
-	/* Never returns Here */
-}
-
-/* Place Holders */
-void board_init_r(gd_t *id, ulong dest_addr)
-{
-	/* Function attribute is no-return */
-	/* This Function never executes */
-	while (1)
-		;
-}
-
-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h
deleted file mode 100644
index 926a4cc..0000000
--- a/board/samsung/origen/origen_setup.h
+++ /dev/null
@@ -1,607 +0,0 @@
-/*
- * Machine Specific Values for ORIGEN board based on S5PV310
- *
- * Copyright (C) 2011 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ORIGEN_SETUP_H
-#define _ORIGEN_SETUP_H
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-
-/* Offsets of clock registers (sources and dividers) */
-#define CLK_SRC_CPU_OFFSET	0x14200
-#define CLK_DIV_CPU0_OFFSET	0x14500
-#define CLK_DIV_CPU1_OFFSET	0x14504
-
-#define CLK_SRC_DMC_OFFSET	0x10200
-#define CLK_DIV_DMC0_OFFSET	0x10500
-#define CLK_DIV_DMC1_OFFSET	0x10504
-
-#define CLK_SRC_TOP0_OFFSET	0xC210
-#define CLK_SRC_TOP1_OFFSET	0xC214
-#define CLK_DIV_TOP_OFFSET	0xC510
-
-#define CLK_SRC_LEFTBUS_OFFSET	0x4200
-#define CLK_DIV_LEFTBUS_OFFSET	0x4500
-
-#define CLK_SRC_RIGHTBUS_OFFSET	0x8200
-#define CLK_DIV_RIGHTBUS_OFFSET	0x8500
-
-#define CLK_SRC_FSYS_OFFSET	0xC240
-#define CLK_DIV_FSYS1_OFFSET	0xC544
-#define CLK_DIV_FSYS2_OFFSET	0xC548
-#define CLK_DIV_FSYS3_OFFSET	0xC54C
-
-#define CLK_SRC_CAM_OFFSET	0xC220
-#define CLK_SRC_TV_OFFSET	0xC224
-#define CLK_SRC_MFC_OFFSET	0xC228
-#define CLK_SRC_G3D_OFFSET	0xC22C
-#define CLK_SRC_LCD0_OFFSET	0xC234
-#define CLK_SRC_PERIL0_OFFSET	0xC250
-
-#define CLK_DIV_CAM_OFFSET	0xC520
-#define CLK_DIV_TV_OFFSET	0xC524
-#define CLK_DIV_MFC_OFFSET	0xC528
-#define CLK_DIV_G3D_OFFSET	0xC52C
-#define CLK_DIV_LCD0_OFFSET	0xC534
-#define CLK_DIV_PERIL0_OFFSET	0xC550
-
-#define CLK_SRC_LCD0_OFFSET	0xC234
-
-#define APLL_LOCK_OFFSET	0x14000
-#define MPLL_LOCK_OFFSET	0x14008
-#define APLL_CON0_OFFSET	0x14100
-#define APLL_CON1_OFFSET	0x14104
-#define MPLL_CON0_OFFSET	0x14108
-#define MPLL_CON1_OFFSET	0x1410C
-
-#define EPLL_LOCK_OFFSET	0xC010
-#define VPLL_LOCK_OFFSET	0xC020
-#define EPLL_CON0_OFFSET	0xC110
-#define EPLL_CON1_OFFSET	0xC114
-#define VPLL_CON0_OFFSET	0xC120
-#define VPLL_CON1_OFFSET	0xC124
-
-/* DMC: DRAM Controllor Register offsets */
-#define DMC_CONCONTROL		0x00
-#define DMC_MEMCONTROL		0x04
-#define DMC_MEMCONFIG0		0x08
-#define DMC_MEMCONFIG1		0x0C
-#define DMC_DIRECTCMD		0x10
-#define DMC_PRECHCONFIG		0x14
-#define DMC_PHYCONTROL0		0x18
-#define DMC_PHYCONTROL1		0x1C
-#define DMC_PHYCONTROL2		0x20
-#define DMC_TIMINGAREF		0x30
-#define DMC_TIMINGROW		0x34
-#define DMC_TIMINGDATA		0x38
-#define DMC_TIMINGPOWER		0x3C
-#define DMC_PHYZQCONTROL	0x44
-
-/* Bus Configuration Register Address */
-#define ASYNC_CONFIG		0x10010350
-
-/* MIU Config Register Offsets*/
-#define APB_SFR_INTERLEAVE_CONF_OFFSET	0x400
-#define APB_SFR_ARBRITATION_CONF_OFFSET		0xC00
-
-/* Offset for inform registers */
-#define INFORM0_OFFSET			0x800
-#define INFORM1_OFFSET			0x804
-
-/* GPIO Offsets for UART: GPIO Contol Register */
-#define EXYNOS4_GPIO_A0_CON_OFFSET	0x00
-#define EXYNOS4_GPIO_A1_CON_OFFSET	0x20
-
-/* UART Register offsets */
-#define ULCON_OFFSET		0x00
-#define UCON_OFFSET		0x04
-#define UFCON_OFFSET		0x08
-#define UBRDIV_OFFSET		0x28
-#define UFRACVAL_OFFSET		0x2C
-
-/* CLK_SRC_CPU */
-#define MUX_HPM_SEL_MOUTAPLL		0x0
-#define MUX_HPM_SEL_SCLKMPLL		0x1
-#define MUX_CORE_SEL_MOUTAPLL		0x0
-#define MUX_CORE_SEL_SCLKMPLL		0x1
-#define MUX_MPLL_SEL_FILPLL		0x0
-#define MUX_MPLL_SEL_MOUTMPLLFOUT	0x1
-#define MUX_APLL_SEL_FILPLL		0x0
-#define MUX_APLL_SEL_MOUTMPLLFOUT	0x1
-#define CLK_SRC_CPU_VAL			((MUX_HPM_SEL_MOUTAPLL << 20) \
-					| (MUX_CORE_SEL_MOUTAPLL << 16) \
-					| (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
-					| (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
-
-/* CLK_DIV_CPU0 */
-#define APLL_RATIO		0x0
-#define PCLK_DBG_RATIO		0x1
-#define ATB_RATIO		0x3
-#define PERIPH_RATIO		0x3
-#define COREM1_RATIO		0x7
-#define COREM0_RATIO		0x3
-#define CORE_RATIO		0x0
-#define CLK_DIV_CPU0_VAL	((APLL_RATIO << 24) \
-				| (PCLK_DBG_RATIO << 20) \
-				| (ATB_RATIO << 16) \
-				| (PERIPH_RATIO << 12) \
-				| (COREM1_RATIO << 8) \
-				| (COREM0_RATIO << 4) \
-				| (CORE_RATIO << 0))
-
-/* CLK_DIV_CPU1 */
-#define HPM_RATIO		0x0
-#define COPY_RATIO		0x3
-#define CLK_DIV_CPU1_VAL	((HPM_RATIO << 4) | (COPY_RATIO))
-
-/* CLK_SRC_DMC */
-#define MUX_PWI_SEL_XXTI		0x0
-#define MUX_PWI_SEL_XUSBXTI		0x1
-#define MUX_PWI_SEL_SCLK_HDMI24M	0x2
-#define MUX_PWI_SEL_SCLK_USBPHY0	0x3
-#define MUX_PWI_SEL_SCLK_USBPHY1	0x4
-#define MUX_PWI_SEL_SCLK_HDMIPHY	0x5
-#define MUX_PWI_SEL_SCLKMPLL		0x6
-#define MUX_PWI_SEL_SCLKEPLL		0x7
-#define MUX_PWI_SEL_SCLKVPLL		0x8
-#define MUX_DPHY_SEL_SCLKMPLL		0x0
-#define MUX_DPHY_SEL_SCLKAPLL		0x1
-#define MUX_DMC_BUS_SEL_SCLKMPLL	0x0
-#define MUX_DMC_BUS_SEL_SCLKAPLL	0x1
-#define CLK_SRC_DMC_VAL			((MUX_PWI_SEL_XUSBXTI << 16) \
-					| (MUX_DPHY_SEL_SCLKMPLL << 8) \
-					| (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
-
-/* CLK_DIV_DMC0 */
-#define CORE_TIMERS_RATIO	0x1
-#define COPY2_RATIO		0x3
-#define DMCP_RATIO		0x1
-#define DMCD_RATIO		0x1
-#define DMC_RATIO		0x1
-#define DPHY_RATIO		0x1
-#define ACP_PCLK_RATIO		0x1
-#define ACP_RATIO		0x3
-#define CLK_DIV_DMC0_VAL	((CORE_TIMERS_RATIO << 28) \
-				| (COPY2_RATIO << 24) \
-				| (DMCP_RATIO << 20) \
-				| (DMCD_RATIO << 16) \
-				| (DMC_RATIO << 12) \
-				| (DPHY_RATIO << 8) \
-				| (ACP_PCLK_RATIO << 4)	\
-				| (ACP_RATIO << 0))
-
-/* CLK_DIV_DMC1 */
-#define DPM_RATIO		0x1
-#define DVSEM_RATIO		0x1
-#define PWI_RATIO		0x1
-#define CLK_DIV_DMC1_VAL	((DPM_RATIO << 24) \
-				| (DVSEM_RATIO << 16) \
-				| (PWI_RATIO << 8))
-
-/* CLK_SRC_TOP0 */
-#define MUX_ONENAND_SEL_ACLK_133	0x0
-#define MUX_ONENAND_SEL_ACLK_160	0x1
-#define MUX_ACLK_133_SEL_SCLKMPLL	0x0
-#define MUX_ACLK_133_SEL_SCLKAPLL	0x1
-#define MUX_ACLK_160_SEL_SCLKMPLL	0x0
-#define MUX_ACLK_160_SEL_SCLKAPLL	0x1
-#define MUX_ACLK_100_SEL_SCLKMPLL	0x0
-#define MUX_ACLK_100_SEL_SCLKAPLL	0x1
-#define MUX_ACLK_200_SEL_SCLKMPLL	0x0
-#define MUX_ACLK_200_SEL_SCLKAPLL	0x1
-#define MUX_VPLL_SEL_FINPLL		0x0
-#define MUX_VPLL_SEL_FOUTVPLL		0x1
-#define MUX_EPLL_SEL_FINPLL		0x0
-#define MUX_EPLL_SEL_FOUTEPLL		0x1
-#define MUX_ONENAND_1_SEL_MOUTONENAND	0x0
-#define MUX_ONENAND_1_SEL_SCLKVPLL	0x1
-#define CLK_SRC_TOP0_VAL		((MUX_ONENAND_SEL_ACLK_133 << 28) \
-					| (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
-					| (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
-					| (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
-					| (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
-					| (MUX_VPLL_SEL_FINPLL << 8) \
-					| (MUX_EPLL_SEL_FINPLL << 4)\
-					| (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
-
-/* CLK_SRC_TOP1 */
-#define VPLLSRC_SEL_FINPLL	0x0
-#define VPLLSRC_SEL_SCLKHDMI24M	0x1
-#define CLK_SRC_TOP1_VAL	(VPLLSRC_SEL_FINPLL)
-
-/* CLK_DIV_TOP */
-#define ONENAND_RATIO		0x0
-#define ACLK_133_RATIO		0x5
-#define ACLK_160_RATIO		0x4
-#define ACLK_100_RATIO		0x7
-#define ACLK_200_RATIO		0x3
-#define CLK_DIV_TOP_VAL		((ONENAND_RATIO << 16)	\
-				| (ACLK_133_RATIO << 12)\
-				| (ACLK_160_RATIO << 8)	\
-				| (ACLK_100_RATIO << 4)	\
-				| (ACLK_200_RATIO << 0))
-
-/* CLK_SRC_LEFTBUS */
-#define MUX_GDL_SEL_SCLKMPLL	0x0
-#define MUX_GDL_SEL_SCLKAPLL	0x1
-#define CLK_SRC_LEFTBUS_VAL	(MUX_GDL_SEL_SCLKMPLL)
-
-/* CLK_DIV_LEFTBUS */
-#define GPL_RATIO		0x1
-#define GDL_RATIO		0x3
-#define CLK_DIV_LEFTBUS_VAL	((GPL_RATIO << 4) | (GDL_RATIO))
-
-/* CLK_SRC_RIGHTBUS */
-#define MUX_GDR_SEL_SCLKMPLL	0x0
-#define MUX_GDR_SEL_SCLKAPLL	0x1
-#define CLK_SRC_RIGHTBUS_VAL	(MUX_GDR_SEL_SCLKMPLL)
-
-/* CLK_DIV_RIGHTBUS */
-#define GPR_RATIO		0x1
-#define GDR_RATIO		0x3
-#define CLK_DIV_RIGHTBUS_VAL	((GPR_RATIO << 4) | (GDR_RATIO))
-
-/* CLK_SRS_FSYS: 6 = SCLKMPLL */
-#define SATA_SEL_SCLKMPLL	0
-#define SATA_SEL_SCLKAPLL	1
-
-#define MMC_SEL_XXTI		0
-#define MMC_SEL_XUSBXTI		1
-#define MMC_SEL_SCLK_HDMI24M	2
-#define MMC_SEL_SCLK_USBPHY0	3
-#define MMC_SEL_SCLK_USBPHY1	4
-#define MMC_SEL_SCLK_HDMIPHY	5
-#define MMC_SEL_SCLKMPLL	6
-#define MMC_SEL_SCLKEPLL	7
-#define MMC_SEL_SCLKVPLL	8
-
-#define MMCC0_SEL		MMC_SEL_SCLKMPLL
-#define MMCC1_SEL		MMC_SEL_SCLKMPLL
-#define MMCC2_SEL		MMC_SEL_SCLKMPLL
-#define MMCC3_SEL		MMC_SEL_SCLKMPLL
-#define MMCC4_SEL		MMC_SEL_SCLKMPLL
-#define CLK_SRC_FSYS_VAL	((SATA_SEL_SCLKMPLL << 24) \
-				| (MMCC4_SEL << 16) \
-				| (MMCC3_SEL << 12) \
-				| (MMCC2_SEL << 8) \
-				| (MMCC1_SEL << 4) \
-				| (MMCC0_SEL << 0))
-
-/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
-/* CLK_DIV_FSYS1 */
-#define MMC0_RATIO		0xF
-#define MMC0_PRE_RATIO		0x0
-#define MMC1_RATIO		0xF
-#define MMC1_PRE_RATIO		0x0
-#define CLK_DIV_FSYS1_VAL	((MMC1_PRE_RATIO << 24) \
-				| (MMC1_RATIO << 16) \
-				| (MMC0_PRE_RATIO << 8) \
-				| (MMC0_RATIO << 0))
-
-/* CLK_DIV_FSYS2 */
-#define MMC2_RATIO		0xF
-#define MMC2_PRE_RATIO		0x0
-#define MMC3_RATIO		0xF
-#define MMC3_PRE_RATIO		0x0
-#define CLK_DIV_FSYS2_VAL	((MMC3_PRE_RATIO << 24) \
-				| (MMC3_RATIO << 16) \
-				| (MMC2_PRE_RATIO << 8) \
-				| (MMC2_RATIO << 0))
-
-/* CLK_DIV_FSYS3 */
-#define MMC4_RATIO		0xF
-#define MMC4_PRE_RATIO		0x0
-#define CLK_DIV_FSYS3_VAL	((MMC4_PRE_RATIO << 8) \
-				| (MMC4_RATIO << 0))
-
-/* CLK_SRC_PERIL0 */
-#define UART_SEL_XXTI		0
-#define UART_SEL_XUSBXTI	1
-#define UART_SEL_SCLK_HDMI24M	2
-#define UART_SEL_SCLK_USBPHY0	3
-#define UART_SEL_SCLK_USBPHY1	4
-#define UART_SEL_SCLK_HDMIPHY	5
-#define UART_SEL_SCLKMPLL	6
-#define UART_SEL_SCLKEPLL	7
-#define UART_SEL_SCLKVPLL	8
-
-#define UART0_SEL		UART_SEL_SCLKMPLL
-#define UART1_SEL		UART_SEL_SCLKMPLL
-#define UART2_SEL		UART_SEL_SCLKMPLL
-#define UART3_SEL		UART_SEL_SCLKMPLL
-#define UART4_SEL		UART_SEL_SCLKMPLL
-#define CLK_SRC_PERIL0_VAL	((UART4_SEL << 16) \
-				| (UART3_SEL << 12) \
-				| (UART2_SEL << 8) \
-				| (UART1_SEL << 4) \
-				| (UART0_SEL << 0))
-
-/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
-/* CLK_DIV_PERIL0 */
-#define UART0_RATIO		7
-#define UART1_RATIO		7
-#define UART2_RATIO		7
-#define UART3_RATIO		7
-#define UART4_RATIO		7
-#define CLK_DIV_PERIL0_VAL	((UART4_RATIO << 16) \
-				| (UART3_RATIO << 12) \
-				| (UART2_RATIO << 8) \
-				| (UART1_RATIO << 4) \
-				| (UART0_RATIO << 0))
-
-/* Clock Source CAM/FIMC */
-/* CLK_SRC_CAM */
-#define CAM0_SEL_XUSBXTI	1
-#define CAM1_SEL_XUSBXTI	1
-#define CSIS0_SEL_XUSBXTI	1
-#define CSIS1_SEL_XUSBXTI	1
-
-#define FIMC_SEL_SCLKMPLL	6
-#define FIMC0_LCLK_SEL		FIMC_SEL_SCLKMPLL
-#define FIMC1_LCLK_SEL		FIMC_SEL_SCLKMPLL
-#define FIMC2_LCLK_SEL		FIMC_SEL_SCLKMPLL
-#define FIMC3_LCLK_SEL		FIMC_SEL_SCLKMPLL
-
-#define CLK_SRC_CAM_VAL		((CSIS1_SEL_XUSBXTI << 28) \
-				| (CSIS0_SEL_XUSBXTI << 24) \
-				| (CAM1_SEL_XUSBXTI << 20) \
-				| (CAM0_SEL_XUSBXTI << 16) \
-				| (FIMC3_LCLK_SEL << 12) \
-				| (FIMC2_LCLK_SEL << 8) \
-				| (FIMC1_LCLK_SEL << 4) \
-				| (FIMC0_LCLK_SEL << 0))
-
-/* SCLK CAM */
-/* CLK_DIV_CAM */
-#define FIMC0_LCLK_RATIO	4
-#define FIMC1_LCLK_RATIO	4
-#define FIMC2_LCLK_RATIO	4
-#define FIMC3_LCLK_RATIO	4
-#define CLK_DIV_CAM_VAL		((FIMC3_LCLK_RATIO << 12) \
-				| (FIMC2_LCLK_RATIO << 8) \
-				| (FIMC1_LCLK_RATIO << 4) \
-				| (FIMC0_LCLK_RATIO << 0))
-
-/* SCLK MFC */
-/* CLK_SRC_MFC */
-#define MFC_SEL_MPLL		0
-#define MOUTMFC_0		0
-#define MFC_SEL			MOUTMFC_0
-#define MFC_0_SEL		MFC_SEL_MPLL
-#define CLK_SRC_MFC_VAL		((MFC_SEL << 8) | (MFC_0_SEL))
-
-
-/* CLK_DIV_MFC */
-#define MFC_RATIO		3
-#define CLK_DIV_MFC_VAL		(MFC_RATIO)
-
-/* SCLK G3D */
-/* CLK_SRC_G3D */
-#define G3D_SEL_MPLL		0
-#define MOUTG3D_0		0
-#define G3D_SEL			MOUTG3D_0
-#define G3D_0_SEL		G3D_SEL_MPLL
-#define CLK_SRC_G3D_VAL		((G3D_SEL << 8) | (G3D_0_SEL))
-
-/* CLK_DIV_G3D */
-#define G3D_RATIO		1
-#define CLK_DIV_G3D_VAL		(G3D_RATIO)
-
-/* SCLK LCD0 */
-/* CLK_SRC_LCD0 */
-#define FIMD_SEL_SCLKMPLL	6
-#define MDNIE0_SEL_XUSBXTI	1
-#define MDNIE_PWM0_SEL_XUSBXTI	1
-#define MIPI0_SEL_XUSBXTI	1
-#define CLK_SRC_LCD0_VAL	((MIPI0_SEL_XUSBXTI << 12) \
-				| (MDNIE_PWM0_SEL_XUSBXTI << 8) \
-				| (MDNIE0_SEL_XUSBXTI << 4) \
-				| (FIMD_SEL_SCLKMPLL << 0))
-
-/* CLK_DIV_LCD0 */
-#define FIMD0_RATIO		4
-#define CLK_DIV_LCD0_VAL	(FIMD0_RATIO)
-
-/* Required period to generate a stable clock output */
-/* PLL_LOCK_TIME */
-#define PLL_LOCKTIME		0x1C20
-
-/* PLL Values */
-#define DISABLE			0
-#define ENABLE			1
-#define SET_PLL(mdiv, pdiv, sdiv)	((ENABLE << 31)\
-					| (mdiv << 16) \
-					| (pdiv << 8) \
-					| (sdiv << 0))
-
-/* APLL_CON0 */
-#define APLL_MDIV		0xFA
-#define APLL_PDIV		0x6
-#define APLL_SDIV		0x1
-#define APLL_CON0_VAL		SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
-
-/* APLL_CON1 */
-#define APLL_AFC_ENB		0x1
-#define APLL_AFC		0xC
-#define APLL_CON1_VAL		((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
-
-/* MPLL_CON0 */
-#define MPLL_MDIV		0xC8
-#define MPLL_PDIV		0x6
-#define MPLL_SDIV		0x1
-#define MPLL_CON0_VAL		SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
-
-/* MPLL_CON1 */
-#define MPLL_AFC_ENB		0x0
-#define MPLL_AFC		0x1C
-#define MPLL_CON1_VAL		((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
-
-/* EPLL_CON0 */
-#define EPLL_MDIV		0x30
-#define EPLL_PDIV		0x3
-#define EPLL_SDIV		0x2
-#define EPLL_CON0_VAL		SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
-
-/* EPLL_CON1 */
-#define EPLL_K			0x0
-#define EPLL_CON1_VAL		(EPLL_K >> 0)
-
-/* VPLL_CON0 */
-#define VPLL_MDIV		0x35
-#define VPLL_PDIV		0x3
-#define VPLL_SDIV		0x2
-#define VPLL_CON0_VAL		SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
-
-/* VPLL_CON1 */
-#define VPLL_SSCG_EN		DISABLE
-#define VPLL_SEL_PF_DN_SPREAD	0x0
-#define VPLL_MRR		0x11
-#define VPLL_MFR		0x0
-#define VPLL_K			0x400
-#define VPLL_CON1_VAL		((VPLL_SSCG_EN << 31)\
-				| (VPLL_SEL_PF_DN_SPREAD << 29) \
-				| (VPLL_MRR << 24) \
-				| (VPLL_MFR << 16) \
-				| (VPLL_K << 0))
-/*
- * UART GPIO_A0/GPIO_A1 Control Register Value
- * 0x2: UART Function
- */
-#define EXYNOS4_GPIO_A0_CON_VAL	0x22222222
-#define EXYNOS4_GPIO_A1_CON_VAL	0x222222
-
-/* ULCON: UART Line Control Value 8N1 */
-#define WORD_LEN_5_BIT		0x00
-#define WORD_LEN_6_BIT		0x01
-#define WORD_LEN_7_BIT		0x02
-#define WORD_LEN_8_BIT		0x03
-
-#define STOP_BIT_1		0x00
-#define STOP_BIT_2		0x01
-
-#define NO_PARITY			0x00
-#define ODD_PARITY			0x4
-#define EVEN_PARITY			0x5
-#define FORCED_PARITY_CHECK_AS_1	0x6
-#define FORCED_PARITY_CHECK_AS_0	0x7
-
-#define INFRAMODE_NORMAL		0x00
-#define INFRAMODE_INFRARED		0x01
-
-#define ULCON_VAL		((INFRAMODE_NORMAL << 6) \
-				| (NO_PARITY << 3) \
-				| (STOP_BIT_1 << 2) \
-				| (WORD_LEN_8_BIT << 0))
-
-/*
- * UCON: UART Control Value
- * Tx_interrupt Type: Level
- * Rx_interrupt Type: Level
- * Rx Timeout Enabled: Yes
- * Rx-Error Atatus_Int Enable: Yes
- * Loop_Back: No
- * Break Signal: No
- * Transmit mode : Interrupt request/polling
- * Receive mode : Interrupt request/polling
- */
-#define TX_PULSE_INTERRUPT	0
-#define TX_LEVEL_INTERRUPT	1
-#define RX_PULSE_INTERRUPT	0
-#define RX_LEVEL_INTERRUPT	1
-
-#define RX_TIME_OUT		ENABLE
-#define RX_ERROR_STATE_INT_ENB	ENABLE
-#define LOOP_BACK		DISABLE
-#define BREAK_SIGNAL		DISABLE
-
-#define TX_MODE_DISABLED	0X00
-#define TX_MODE_IRQ_OR_POLL	0X01
-#define TX_MODE_DMA		0X02
-
-#define RX_MODE_DISABLED	0X00
-#define RX_MODE_IRQ_OR_POLL	0X01
-#define RX_MODE_DMA		0X02
-
-#define UCON_VAL		((TX_LEVEL_INTERRUPT << 9) \
-				| (RX_LEVEL_INTERRUPT << 8) \
-				| (RX_TIME_OUT << 7) \
-				| (RX_ERROR_STATE_INT_ENB << 6) \
-				| (LOOP_BACK << 5) \
-				| (BREAK_SIGNAL << 4) \
-				| (TX_MODE_IRQ_OR_POLL << 2) \
-				| (RX_MODE_IRQ_OR_POLL << 0))
-
-/*
- * UFCON: UART FIFO Control Value
- * Tx FIFO Trigger LEVEL: 2 Bytes (001)
- * Rx FIFO Trigger LEVEL: 2 Bytes (001)
- * Tx Fifo Reset: No
- * Rx Fifo Reset: No
- * FIFO Enable: Yes
- */
-#define TX_FIFO_TRIGGER_LEVEL_0_BYTES	0x00
-#define TX_FIFO_TRIGGER_LEVEL_2_BYTES	0x1
-#define TX_FIFO_TRIGGER_LEVEL_4_BYTES	0x2
-#define TX_FIFO_TRIGGER_LEVEL_6_BYTES	0x3
-#define TX_FIFO_TRIGGER_LEVEL_8_BYTES	0x4
-#define TX_FIFO_TRIGGER_LEVEL_10_BYTES	0x5
-#define TX_FIFO_TRIGGER_LEVEL_12_BYTES	0x6
-#define TX_FIFO_TRIGGER_LEVEL_14_BYTES	0x7
-
-#define RX_FIFO_TRIGGER_LEVEL_2_BYTES	0x0
-#define RX_FIFO_TRIGGER_LEVEL_4_BYTES	0x1
-#define RX_FIFO_TRIGGER_LEVEL_6_BYTES	0x2
-#define RX_FIFO_TRIGGER_LEVEL_8_BYTES	0x3
-#define RX_FIFO_TRIGGER_LEVEL_10_BYTES	0x4
-#define RX_FIFO_TRIGGER_LEVEL_12_BYTES	0x5
-#define RX_FIFO_TRIGGER_LEVEL_14_BYTES	0x6
-#define RX_FIFO_TRIGGER_LEVEL_16_BYTES	0x7
-
-#define TX_FIFO_TRIGGER_LEVEL		TX_FIFO_TRIGGER_LEVEL_2_BYTES
-#define RX_FIFO_TRIGGER_LEVEL		RX_FIFO_TRIGGER_LEVEL_4_BYTES
-#define TX_FIFO_RESET			DISABLE
-#define RX_FIFO_RESET			DISABLE
-#define FIFO_ENABLE			ENABLE
-#define UFCON_VAL			((TX_FIFO_TRIGGER_LEVEL << 8) \
-					| (RX_FIFO_TRIGGER_LEVEL << 4) \
-					| (TX_FIFO_RESET << 2) \
-					| (RX_FIFO_RESET << 1) \
-					| (FIFO_ENABLE << 0))
-/*
- * Baud Rate Division Value
- * 115200 BAUD:
- * UBRDIV_VAL = SCLK_UART/((115200 * 16) - 1)
- * UBRDIV_VAL = (800 MHz)/((115200 * 16) - 1)
- */
-#define UBRDIV_VAL		0x35
-
-/*
- * Fractional Part of Baud Rate Divisor:
- * 115200 BAUD:
- * UBRFRACVAL = ((((SCLK_UART*10/(115200*16) -10))%10)*16/10)
- * UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
- */
-#define UFRACVAL_VAL		0x4
-#endif