rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

2 files changed, 15 insertions, 15 deletions

diff --git a/board/rsdproto/flash.c b/board/rsdproto/flash.c
index 312b400..e99c2a6 100644
--- a/board/rsdproto/flash.c
+++ b/board/rsdproto/flash.c
@@ -41,7 +41,7 @@
  */
 #undef WITH_AUTOSELECT
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 #if 1
 #define D(x)
@@ -94,7 +94,7 @@ unsigned long flash_init (void)
 #endif
 
     /* Init: no FLASHes known */
-    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+    for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
     }
 
@@ -120,14 +120,14 @@ unsigned long flash_init (void)
 	 * protect monitor and environment sectors
 	 */
 
-#if CFG_MONITOR_BASE >= PHYS_FLASH
+#if CONFIG_SYS_MONITOR_BASE >= PHYS_FLASH
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[1]);
 #endif
 
@@ -259,7 +259,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	start = get_timer (0);
 	do
 	{
-		if (get_timer(start) > CFG_FLASH_ERASE_TOUT)
+		if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT)
 		{	/* write reset command, command address is unimportant */
 			/* this command turns the flash back to read mode     */
 			f_addr =
@@ -387,7 +387,7 @@ static unsigned char write_ull(flash_info_t *info,
 	start = get_timer (0);
 	do
 	{
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
 		{
 			/* write reset command, command address is unimportant */
 			/* this command turns the flash back to read mode     */
diff --git a/board/rsdproto/rsdproto.c b/board/rsdproto/rsdproto.c
index eeec3b4..26edb2e 100644
--- a/board/rsdproto/rsdproto.c
+++ b/board/rsdproto/rsdproto.c
@@ -253,7 +253,7 @@ int checkboard (void)
 	puts ("Board: Rohde & Schwarz 8260 Protocol Board\n");
 
 	/* initialise i2c */
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	read_RS5C372_time (&timedate);
 	printf ("  Time:  %02d:%02d:%02d\n",
@@ -284,7 +284,7 @@ int misc_init_f (void)
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
 #ifdef INIT_LOCAL_BUS_SDRAM
@@ -317,7 +317,7 @@ phys_size_t initdram (int board_type)
 		 *
 		 * The appropriate BRx/ORx registers have already
 		 * been set when we get here (see cpu_init_f). The
-		 * SDRAM can be accessed at the address CFG_SDRAM_BASE.
+		 * SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 		 */
 		memctl->memc_mptpr = 0x2000;
 		memctl->memc_mar = 0x0200;
@@ -330,7 +330,7 @@ phys_size_t initdram (int board_type)
 		memctl->memc_lsrt = 0x0b;
 		memctl->memc_lurt = 0x00;
 		ramaddr = (uchar *) PHYS_SDRAM_LOCAL;
-		sdmr = CFG_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
+		sdmr = CONFIG_SYS_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
 		memctl->memc_lsdmr = sdmr | PSDMR_OP_PREA;
 		*ramaddr = 0xff;
 		for (i = 0; i < 8; i++) {
@@ -339,13 +339,13 @@ phys_size_t initdram (int board_type)
 		}
 		memctl->memc_lsdmr = sdmr | PSDMR_OP_MRW;
 		*ramaddr = 0xff;
-		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_NORM;
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_NORM;
 #endif
 		/* initialise 60x bus ram */
 		memctl->memc_psrt = 0x0b;
 		memctl->memc_purt = 0x08;
 		ramaddr32 = (ulong *) PHYS_SDRAM_60X;
-		sdmr = CFG_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
+		sdmr = CONFIG_SYS_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
 		memctl->memc_psdmr = sdmr | PSDMR_OP_PREA;
 		ramaddr32[0] = 0x00ff00ff;
 		ramaddr32[1] = 0x00ff00ff;