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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2009-06-12 21:20:37 +0200
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2009-06-21 16:18:11 +0200
commit7a11c7f9747240dc770954d320569596c0fbcb50 (patch)
treeddd05598821864416246612aa2e4552e955b553f /board/ronetix/pm9263/pm9263.c
parent3e88337b225bf796f6df21d0a7f591530e9d4ce0 (diff)
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pm9263: lowlevel init update
move PSRAM init to pm9263.c this will allow us after to make the nor lowlevel_init generic Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'board/ronetix/pm9263/pm9263.c')
-rw-r--r--board/ronetix/pm9263/pm9263.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index d2598a0..8ca71da 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -165,6 +165,27 @@ void lcd_disable(void)
static int pm9263_lcd_hw_psram_init(void)
{
volatile uint16_t x;
+ unsigned long csa;
+
+ /* Enable CS3 3.3v, no pull-ups */
+ csa = at91_sys_read(AT91_MATRIX_EBI1CSA);
+ at91_sys_write(AT91_MATRIX_EBI1CSA,
+ csa | AT91_MATRIX_EBI1_DBPUC |
+ AT91_MATRIX_EBI1_VDDIOMSEL_3_3V);
+
+ /* Configure SMC1 CS0 for PSRAM - 16-bit */
+ at91_sys_write(AT91_SMC1_SETUP(0),
+ AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC1_PULSE(0),
+ AT91_SMC_NWEPULSE_(7) | AT91_SMC_NCS_WRPULSE_(7) |
+ AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(7));
+ at91_sys_write(AT91_SMC1_CYCLE(0),
+ AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
+ at91_sys_write(AT91_SMC1_MODE(0),
+ AT91_SMC_DBW_16 |
+ AT91_SMC_PMEN |
+ AT91_SMC_PS_32);
/* setup PB29 as output */
at91_set_gpio_output(PSRAM_CRE_PIN, 1);