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authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>2014-11-06 15:42:24 +0900
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>2014-11-10 09:44:43 +0900
commitf0261243102fbc020a01178a46a52e00fc55e3d2 (patch)
tree36261debe80058d2d2d9709abe243f5245712338 /board/renesas/gose/gose.c
parent6a994e5bb6ba0193d655e2cd67ff8d93bfe66d82 (diff)
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arm: rmobile: gose: Add Ethernet support
Gose board has one ether port, this works using sh-ether driver. This adds GPIO settings and driver settings in order to use the sh-ether. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'board/renesas/gose/gose.c')
-rw-r--r--board/renesas/gose/gose.c62
1 files changed, 62 insertions, 0 deletions
diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c
index 09905af..2cef701 100644
--- a/board/renesas/gose/gose.c
+++ b/board/renesas/gose/gose.c
@@ -15,6 +15,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
+#include <netdev.h>
+#include <miiphy.h>
#include <i2c.h>
#include "qos.h"
@@ -47,6 +49,10 @@ void s_init(void)
#define SMSTPCR7 0xE615014C
#define SCIF0_MSTP721 (1 << 21)
+#define MSTPSR8 0xE61509A0
+#define SMSTPCR8 0xE6150990
+#define ETHER_MSTP813 (1 << 13)
+
#define mstp_setbits(type, addr, saddr, set) \
out_##type((saddr), in_##type(addr) | (set))
#define mstp_clrbits(type, addr, saddr, clear) \
@@ -64,6 +70,9 @@ int board_early_init_f(void)
/* SCIF0 */
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+ /* ETHER */
+ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
return 0;
}
@@ -77,6 +86,10 @@ void arch_preboot_os(void)
mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
}
+#define PUPR5 0xE6060114
+#define PUPR5_ETH 0x3FFC0000
+#define PUPR5_ETH_MAGIC (1 << 27)
+
int board_init(void)
{
/* adress of boot parameters */
@@ -85,9 +98,58 @@ int board_init(void)
/* Init PFC controller */
r8a7793_pinmux_init();
+ /* ETHER Enable */
+ gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+ gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+ gpio_request(GPIO_FN_ETH_RXD0, NULL);
+ gpio_request(GPIO_FN_ETH_RXD1, NULL);
+ gpio_request(GPIO_FN_ETH_LINK, NULL);
+ gpio_request(GPIO_FN_ETH_REFCLK, NULL);
+ gpio_request(GPIO_FN_ETH_MDIO, NULL);
+ gpio_request(GPIO_FN_ETH_TXD1, NULL);
+ gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+ gpio_request(GPIO_FN_ETH_TXD0, NULL);
+ gpio_request(GPIO_FN_ETH_MDC, NULL);
+ gpio_request(GPIO_FN_IRQ0, NULL);
+
+ mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
+ gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
+ mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
+
+ gpio_direction_output(GPIO_GP_5_22, 0);
+ mdelay(20);
+ gpio_set_value(GPIO_GP_5_22, 1);
+ udelay(1);
+
return 0;
}
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = -ENODEV;
+ u32 val;
+ unsigned char enetaddr[6];
+
+#ifdef CONFIG_SH_ETHER
+ ret = sh_eth_initialize(bis);
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ return ret;
+
+ /* Set Mac address */
+ val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+ enetaddr[2] << 8 | enetaddr[3];
+ writel(val, CXR24);
+
+ val = enetaddr[4] << 8 | enetaddr[5];
+ writel(val, CXR25);
+#endif
+
+ return ret;
+}
+
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;