diff options
| author | wdenk <wdenk> | 2003-06-27 21:31:46 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-06-27 21:31:46 +0000 |
| commit | 8bde7f776c77b343aca29b8c7b58464d915ac245 (patch) | |
| tree | 20f1fd99975215e7c658454a15cdb4ed4694e2d4 /board/rbc823/rbc823.c | |
| parent | 993cad9364c6b87ae429d1ed1130d8153f6f027e (diff) | |
| download | u-boot-imx-8bde7f776c77b343aca29b8c7b58464d915ac245.zip u-boot-imx-8bde7f776c77b343aca29b8c7b58464d915ac245.tar.gz u-boot-imx-8bde7f776c77b343aca29b8c7b58464d915ac245.tar.bz2 | |
* Code cleanup:
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
Diffstat (limited to 'board/rbc823/rbc823.c')
| -rw-r--r-- | board/rbc823/rbc823.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/board/rbc823/rbc823.c b/board/rbc823/rbc823.c index 24ed501..9bb1c1d 100644 --- a/board/rbc823/rbc823.c +++ b/board/rbc823/rbc823.c @@ -151,7 +151,7 @@ long int initdram (int board_type) upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); /* - * 1 Bank of 64Mbit x 2 devices + * 1 Bank of 64Mbit x 2 devices */ memctl->memc_mptpr = CFG_MPTPR_1BK_4K; memctl->memc_mar = 0x00000088; @@ -164,8 +164,8 @@ long int initdram (int board_type) memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay(200); - /* - * Perform SDRAM initializsation sequence + /* + * Perform SDRAM initializsation sequence */ memctl->memc_mcr = 0x80008105; /* SDRAM bank 0 */ udelay(1); @@ -174,7 +174,7 @@ long int initdram (int board_type) memctl->memc_mcr = 0x80008130; /* SDRAM bank 0 - execute twice */ udelay(1); memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X; - udelay(200); + udelay(200); memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ udelay (1000); @@ -185,7 +185,7 @@ long int initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; // 16: but should be: CFG_MPTPR_1BK_4K + memctl->memc_mptpr = CFG_MPTPR_2BK_4K; /* 16: but should be: CFG_MPTPR_1BK_4K */ /* * Check Bank 0 Memory Size for re-configuration @@ -289,4 +289,3 @@ void doc_init(void) doc_probe(FLASH_BASE1_PRELIM); } - |