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authorJon Loeliger <jdl@freescale.com>2008-07-10 12:05:32 -0500
committerJon Loeliger <jdl@freescale.com>2008-07-10 12:05:32 -0500
commit859f24350e6e4313626f85161dd03f025a4dac59 (patch)
treea025f68619045556e662326c8e1cbc147f9b633e /board/r7780mp/r7780mp.c
parent3473ab737282b08ad61841fcbb14c4d264a93a8e (diff)
parente0320b1ebec13755911a53b0af12cbf3e5e49a65 (diff)
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Merge commit 'wd/master'
Diffstat (limited to 'board/r7780mp/r7780mp.c')
-rw-r--r--board/r7780mp/r7780mp.c22
1 files changed, 10 insertions, 12 deletions
diff --git a/board/r7780mp/r7780mp.c b/board/r7780mp/r7780mp.c
index 1a37711..19c35d3 100644
--- a/board/r7780mp/r7780mp.c
+++ b/board/r7780mp/r7780mp.c
@@ -38,12 +38,12 @@ int checkboard(void)
int board_init(void)
{
/* SCIF Enable */
- *(vu_short*)PHCR = 0x0000;
+ writew(0x0, PHCR);
return 0;
}
-int dram_init (void)
+int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
@@ -53,29 +53,27 @@ int dram_init (void)
return 0;
}
-void led_set_state (unsigned short value)
+void led_set_state(unsigned short value)
{
}
-void ide_set_reset (int idereset)
+void ide_set_reset(int idereset)
{
/* if reset = 1 IDE reset will be asserted */
- if (idereset){
- (*(vu_short *)FPGA_CFCTL) = 0x432;
+ if (idereset) {
+ writew(0x432, FPGA_CFCTL);
#if defined(CONFIG_R7780MP)
- (*(vu_short *)FPGA_CFPOW) |= 0x01;
+ writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW);
#else
- (*(vu_short *)FPGA_CFPOW) |= 0x02;
+ writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW);
#endif
- (*(vu_short *)FPGA_CFCDINTCLR) = 0x01;
+ writew(0x01, FPGA_CFCDINTCLR);
}
}
-#if defined(CONFIG_PCI)
static struct pci_controller hose;
void pci_init_board(void)
{
- pci_sh7780_init( &hose );
+ pci_sh7780_init(&hose);
}
-#endif