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authorStefan Roese <sr@denx.de>2008-07-10 09:09:45 +0200
committerStefan Roese <sr@denx.de>2008-07-10 09:09:45 +0200
commitac5ba41c2234dd513ed2c879914e964cc05a0135 (patch)
treeeea25003c17267efc504264bc1faa419a355a138 /board/r2dplus/r2dplus.c
parent7c6237b3e2f2ee0098897da39b79aff4642b8946 (diff)
parent4188f0491886b3b486164e819c0a83fdb97efd7d (diff)
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Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'board/r2dplus/r2dplus.c')
-rw-r--r--board/r2dplus/r2dplus.c28
1 files changed, 15 insertions, 13 deletions
diff --git a/board/r2dplus/r2dplus.c b/board/r2dplus/r2dplus.c
index 2ee3ea2..8fb8ff6 100644
--- a/board/r2dplus/r2dplus.c
+++ b/board/r2dplus/r2dplus.c
@@ -24,6 +24,7 @@
#include <common.h>
#include <ide.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <asm/pci.h>
int checkboard(void)
@@ -37,7 +38,7 @@ int board_init(void)
return 0;
}
-int dram_init (void)
+int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
@@ -52,25 +53,26 @@ int board_late_init(void)
return 0;
}
-#define FPGA_BASE 0xA4000000
-#define FPGA_CFCTL (FPGA_BASE + 0x04)
-#define FPGA_CFPOW (FPGA_BASE + 0x06)
-#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A)
+#define FPGA_BASE 0xA4000000
+#define FPGA_CFCTL (FPGA_BASE + 0x04)
+#define CFCTL_EN (0x432)
+#define FPGA_CFPOW (FPGA_BASE + 0x06)
+#define CFPOW_ON (0x02)
+#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A)
+#define CFCDINTCLR_EN (0x01)
-void ide_set_reset (int idereset)
+void ide_set_reset(int idereset)
{
/* if reset = 1 IDE reset will be asserted */
- if (idereset){
- (*(vu_short *)FPGA_CFCTL) = 0x432;
- (*(vu_short *)FPGA_CFPOW) |= 0x02;
- (*(vu_short *)FPGA_CFCDINTCLR) = 0x01;
+ if (idereset) {
+ outw(CFCTL_EN, FPGA_CFCTL); /* CF enable */
+ outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */
+ outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */
}
}
-#if defined(CONFIG_PCI)
static struct pci_controller hose;
void pci_init_board(void)
{
- pci_sh7751_init( &hose );
+ pci_sh7751_init(&hose);
}
-#endif /* CONFIG_PCI */