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| author | Eric Sun <jian.sun@freescale.com> | 2012-05-18 19:57:41 +0800 |
|---|---|---|
| committer | Eric Sun <jian.sun@freescale.com> | 2012-05-18 20:05:39 +0800 |
| commit | 9b6dfc4b6f0d30b7284511a962e64e83c426b854 (patch) | |
| tree | caede78d33459aea738d837a3ccfe9f7087a1901 /board/qemu-mips | |
| parent | 66a2afd595643732dc374ff0afccd3a64c1505bc (diff) | |
| download | u-boot-imx-9b6dfc4b6f0d30b7284511a962e64e83c426b854.zip u-boot-imx-9b6dfc4b6f0d30b7284511a962e64e83c426b854.tar.gz u-boot-imx-9b6dfc4b6f0d30b7284511a962e64e83c426b854.tar.bz2 | |
ENGR00210014 i.mx6 : i.mx6sl : add PAD_CTL_LVE support for pad configuration
Original pad configuration don't provide enough bitfield width to hold
all necessary information. For MX6Sololite, a "PAD_CTL_LVE" is needed
to be configed for many pins.
iomux_v3_cfg_t is re-orgnized to address this issue. PAD_CTRL is
extended by 1 bit to hold the "PAD_CTL_LVE". Which is mapped to proper
bit location when configure the PAD config register.
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
Diffstat (limited to 'board/qemu-mips')
0 files changed, 0 insertions, 0 deletions