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authorGabor Juhos <juhosg@openwrt.org>2013-05-22 03:57:42 +0000
committerTom Rini <trini@ti.com>2013-07-24 09:51:04 -0400
commitfeaa60662768dcc97fdf7c593583876ce4e1564c (patch)
tree72703233c476cba89131d99c9cc769c3d0d1ba87 /board/qemu-malta
parentac12984de8e2239a19c054ffcc615ad4a2e57cc4 (diff)
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MIPS: qemu-malta: add PCI support
Qemu emulates the Galileo GT64120 System Controller which provides a CPU bus to PCI bus bridge. The patch adds driver for this bridge and enables PCI support for the emulated Malta board. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Diffstat (limited to 'board/qemu-malta')
-rw-r--r--board/qemu-malta/qemu-malta.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/board/qemu-malta/qemu-malta.c b/board/qemu-malta/qemu-malta.c
index 449da9c..e3a733f 100644
--- a/board/qemu-malta/qemu-malta.c
+++ b/board/qemu-malta/qemu-malta.c
@@ -8,8 +8,10 @@
#include <common.h>
+#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/malta.h>
+#include <pci_gt64120.h>
phys_size_t initdram(int board_type)
{
@@ -29,3 +31,13 @@ void _machine_restart(void)
reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
__raw_writel(GORESET, reset_base);
}
+
+void pci_init_board(void)
+{
+ set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE));
+
+ gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
+ 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
+ 0x10000000, 0x10000000, 128 * 1024 * 1024,
+ 0x00000000, 0x00000000, 0x20000);
+}