diff options
| author | Markus Klotzbuecher <mk@denx.de> | 2008-07-10 10:26:07 +0200 |
|---|---|---|
| committer | Markus Klotzbuecher <mk@denx.de> | 2008-07-10 10:26:07 +0200 |
| commit | 794a5924972fc8073616e98a2668da4a5f9aea90 (patch) | |
| tree | dd0db39b3e183b5bcb0300d5377d7a0d5ac5fd0c /board/purple/purple.c | |
| parent | f2aeecc320f5b181b30effcaa67683aec8d5a843 (diff) | |
| parent | 4188f0491886b3b486164e819c0a83fdb97efd7d (diff) | |
| download | u-boot-imx-794a5924972fc8073616e98a2668da4a5f9aea90.zip u-boot-imx-794a5924972fc8073616e98a2668da4a5f9aea90.tar.gz u-boot-imx-794a5924972fc8073616e98a2668da4a5f9aea90.tar.bz2 | |
Merge branch 'master' of git://www.denx.de/git/u-boot
Diffstat (limited to 'board/purple/purple.c')
| -rw-r--r-- | board/purple/purple.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/board/purple/purple.c b/board/purple/purple.c index 89cb906..9775591 100644 --- a/board/purple/purple.c +++ b/board/purple/purple.c @@ -85,16 +85,16 @@ static void sdram_timing_init (ulong size) while (p4 < 32 && done == 0) { WRITE_MC_IOGP_1; - for (addr = KSEG1 + 0x4000; - addr < KSEG1ADDR (size); + for (addr = CKSEG1 + 0x4000; + addr < CKSEG1ADDR (size); addr = addr + 4) { *(uint *) addr = 0xaa55aa55; } pass = 1; - for (addr = KSEG1 + 0x4000; - addr < KSEG1ADDR (size) && pass == 1; + for (addr = CKSEG1 + 0x4000; + addr < CKSEG1ADDR (size) && pass == 1; addr = addr + 4) { if (*(uint *) addr != 0xaa55aa55) pass = 0; @@ -124,7 +124,7 @@ static void sdram_timing_init (ulong size) } } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { /* The only supported number of SDRAM banks is 4. */ @@ -138,7 +138,7 @@ long int initdram(int board_type) ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB; void (* sdram_init) (ulong); - sdram_init = (void (*)(ulong)) KSEG0ADDR(&sdram_timing_init); + sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init); sdram_init(0x10000); @@ -260,14 +260,14 @@ void copy_code (ulong dest_addr) /* flush caches */ - start = KSEG0; + start = CKSEG0; end = start + CFG_DCACHE_SIZE; while(start < end) { cache_unroll(start,Index_Writeback_Inv_D); start += CFG_CACHELINE_SIZE; } - start = KSEG0; + start = CKSEG0; end = start + CFG_ICACHE_SIZE; while(start < end) { cache_unroll(start,Index_Invalidate_I); |