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author | Stefan Roese <sr@denx.de> | 2008-10-21 11:43:08 +0200 |
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committer | Stefan Roese <sr@denx.de> | 2008-10-21 11:43:08 +0200 |
commit | f61f1e150c84f5b9347fca79a4bc5f2286c545d2 (patch) | |
tree | ab90f076f18e56b2b3e8c9375b95917daa78c1d9 /board/pleb2 | |
parent | ec081c2c190148b374e86a795fb6b1c49caeb549 (diff) | |
parent | f82642e33899766892499b163e60560fbbf87773 (diff) | |
download | u-boot-imx-f61f1e150c84f5b9347fca79a4bc5f2286c545d2.zip u-boot-imx-f61f1e150c84f5b9347fca79a4bc5f2286c545d2.tar.gz u-boot-imx-f61f1e150c84f5b9347fca79a4bc5f2286c545d2.tar.bz2 |
Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'board/pleb2')
-rw-r--r-- | board/pleb2/flash.c | 32 | ||||
-rw-r--r-- | board/pleb2/lowlevel_init.S | 84 |
2 files changed, 58 insertions, 58 deletions
diff --git a/board/pleb2/flash.c b/board/pleb2/flash.c index 3f01921..abaf0b4 100644 --- a/board/pleb2/flash.c +++ b/board/pleb2/flash.c @@ -28,7 +28,7 @@ */ #include <environment.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it * has nothing to do with the flash chip being 8-bit or 16-bit. @@ -59,7 +59,7 @@ static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data); static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data); static void flash_get_offsets (ulong base, flash_info_t * info); -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION static void flash_sync_real_protect (flash_info_t * info); #endif @@ -74,11 +74,11 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } - size_b = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]); + size_b = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); flash_info[0].size = size_b; @@ -90,20 +90,20 @@ unsigned long flash_init (void) /* Do this again (was done already in flast_get_size), just * in case we move it when remap the FLASH. */ - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION /* read the hardware protection status (if any) into the * protection array in flash_info. */ flash_sync_real_protect (&flash_info[0]); #endif -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif @@ -418,7 +418,7 @@ ulong flash_get_size (FPWV * addr, flash_info_t * info) return (info->size); } -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION /*----------------------------------------------------------------------- */ @@ -559,7 +559,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { if ((now = - get_timer_masked ()) > CFG_FLASH_ERASE_TOUT) { + get_timer_masked ()) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); if (intel) { @@ -573,7 +573,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) } /* show that we're waiting */ - if ((now - last) > 1 * CFG_HZ) { /* every second */ + if ((now - last) > 1 * CONFIG_SYS_HZ) { /* every second */ putc ('.'); last = now; } @@ -609,7 +609,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) /* combine source and destination data so can program * an entire word of 16 or 32 bits */ -#ifdef CFG_LITTLE_ENDIAN +#ifdef CONFIG_SYS_LITTLE_ENDIAN for (i = 0; i < sizeof (data); i++) { data >>= 8; if (i < bytes || i - bytes >= left) @@ -688,7 +688,7 @@ static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) /* data polling for D7 */ while (res == 0 && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW) 0x00F000F0; /* reset bank */ res = 1; } @@ -733,7 +733,7 @@ static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data) reset_timer_masked (); while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW) 0x00B000B0; /* Suspend program */ res = 1; } @@ -748,7 +748,7 @@ static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data) return (res); } -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION /*----------------------------------------------------------------------- */ int flash_real_protect (flash_info_t * info, long sector, int prot) diff --git a/board/pleb2/lowlevel_init.S b/board/pleb2/lowlevel_init.S index add2c53..b95ff9c 100644 --- a/board/pleb2/lowlevel_init.S +++ b/board/pleb2/lowlevel_init.S @@ -24,7 +24,7 @@ #include <version.h> #include <asm/arch/pxa-regs.h> -DRAM_SIZE: .long CFG_DRAM_SIZE +DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE /* wait for coprocessor write complete */ .macro CPWAIT reg @@ -41,92 +41,92 @@ lowlevel_init: /* Set up GPIO pins first */ ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL + ldr r1, =CONFIG_SYS_GPSR0_VAL str r1, [r0] ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL + ldr r1, =CONFIG_SYS_GPSR1_VAL str r1, [r0] ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL + ldr r1, =CONFIG_SYS_GPSR2_VAL str r1, [r0] ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL + ldr r1, =CONFIG_SYS_GPCR0_VAL str r1, [r0] ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL + ldr r1, =CONFIG_SYS_GPCR1_VAL str r1, [r0] ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL + ldr r1, =CONFIG_SYS_GPCR2_VAL str r1, [r0] ldr r0, =GRER0 - ldr r1, =CFG_GRER0_VAL + ldr r1, =CONFIG_SYS_GRER0_VAL str r1, [r0] ldr r0, =GRER1 - ldr r1, =CFG_GRER1_VAL + ldr r1, =CONFIG_SYS_GRER1_VAL str r1, [r0] ldr r0, =GRER2 - ldr r1, =CFG_GRER2_VAL + ldr r1, =CONFIG_SYS_GRER2_VAL str r1, [r0] ldr r0, =GFER0 - ldr r1, =CFG_GFER0_VAL + ldr r1, =CONFIG_SYS_GFER0_VAL str r1, [r0] ldr r0, =GFER1 - ldr r1, =CFG_GFER1_VAL + ldr r1, =CONFIG_SYS_GFER1_VAL str r1, [r0] ldr r0, =GFER2 - ldr r1, =CFG_GFER2_VAL + ldr r1, =CONFIG_SYS_GFER2_VAL str r1, [r0] ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL + ldr r1, =CONFIG_SYS_GPDR0_VAL str r1, [r0] ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL + ldr r1, =CONFIG_SYS_GPDR1_VAL str r1, [r0] ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL + ldr r1, =CONFIG_SYS_GPDR2_VAL str r1, [r0] ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL + ldr r1, =CONFIG_SYS_GAFR0_L_VAL str r1, [r0] ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL + ldr r1, =CONFIG_SYS_GAFR0_U_VAL str r1, [r0] ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL + ldr r1, =CONFIG_SYS_GAFR1_L_VAL str r1, [r0] ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL + ldr r1, =CONFIG_SYS_GAFR1_U_VAL str r1, [r0] ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL + ldr r1, =CONFIG_SYS_GAFR2_L_VAL str r1, [r0] ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL + ldr r1, =CONFIG_SYS_GAFR2_U_VAL str r1, [r0] /* enable GPIO pins */ ldr r0, =PSSR - ldr r1, =CFG_PSSR_VAL + ldr r1, =CONFIG_SYS_PSSR_VAL str r1, [r0] @@ -161,61 +161,61 @@ mem_init: @ Step 2a @ write msc0, read back to ensure data latches @ - ldr r2, =CFG_MSC0_VAL + ldr r2, =CONFIG_SYS_MSC0_VAL str r2, [r1, #MSC0_OFFSET] ldr r2, [r1, #MSC0_OFFSET] @ write msc1 - ldr r2, =CFG_MSC1_VAL + ldr r2, =CONFIG_SYS_MSC1_VAL str r2, [r1, #MSC1_OFFSET] ldr r2, [r1, #MSC1_OFFSET] @ write msc2 - ldr r2, =CFG_MSC2_VAL + ldr r2, =CONFIG_SYS_MSC2_VAL str r2, [r1, #MSC2_OFFSET] ldr r2, [r1, #MSC2_OFFSET] @ Step 2b @ write mecr - ldr r2, =CFG_MECR_VAL + ldr r2, =CONFIG_SYS_MECR_VAL str r2, [r1, #MECR_OFFSET] @ write mcmem0 - ldr r2, =CFG_MCMEM0_VAL + ldr r2, =CONFIG_SYS_MCMEM0_VAL str r2, [r1, #MCMEM0_OFFSET] @ write mcmem1 - ldr r2, =CFG_MCMEM1_VAL + ldr r2, =CONFIG_SYS_MCMEM1_VAL str r2, [r1, #MCMEM1_OFFSET] @ write mcatt0 - ldr r2, =CFG_MCATT0_VAL + ldr r2, =CONFIG_SYS_MCATT0_VAL str r2, [r1, #MCATT0_OFFSET] @ write mcatt1 - ldr r2, =CFG_MCATT1_VAL + ldr r2, =CONFIG_SYS_MCATT1_VAL str r2, [r1, #MCATT1_OFFSET] @ write mcio0 - ldr r2, =CFG_MCIO0_VAL + ldr r2, =CONFIG_SYS_MCIO0_VAL str r2, [r1, #MCIO0_OFFSET] @ write mcio1 - ldr r2, =CFG_MCIO1_VAL + ldr r2, =CONFIG_SYS_MCIO1_VAL str r2, [r1, #MCIO1_OFFSET] @ Step 2c @ fly-by-dma is defeatured on this part @ write flycnfg - @ldr r2, =CFG_FLYCNFG_VAL + @ldr r2, =CONFIG_SYS_FLYCNFG_VAL @str r2, [r1, #FLYCNFG_OFFSET] /* FIXME Does this sequence really make sense */ #ifdef REDBOOT_WAY @ Step 2d @ get the mdrefr settings - ldr r3, =CFG_MDREFR_VAL + ldr r3, =CONFIG_SYS_MDREFR_VAL @ extract DRI field (we need a valid DRI field) @ @@ -296,7 +296,7 @@ mem_init: #else @ Step 2d @ get the mdrefr settings - ldr r3, =CFG_MDREFR_VAL + ldr r3, =CONFIG_SYS_MDREFR_VAL @ write back mdrefr @ @@ -340,7 +340,7 @@ mem_init: @ Step 4d @ fetch platform value of mdcnfg @ - ldr r2, =CFG_MDCNFG_VAL + ldr r2, =CONFIG_SYS_MDCNFG_VAL @ disable all sdram banks @ @@ -375,7 +375,7 @@ mem_init: @ Access memory *not yet enabled* for CBR refresh cycles (8) @ - CBR is generated for all banks - ldr r2, =CFG_DRAM_BASE + ldr r2, =CONFIG_SYS_DRAM_BASE str r2, [r2] str r2, [r2] str r2, [r2] @@ -405,7 +405,7 @@ mem_init: @ Step 4h @ write mdmrs @ - ldr r2, =CFG_MDMRS_VAL + ldr r2, =CONFIG_SYS_MDMRS_VAL str r2, [r1, #MDMRS_OFFSET] @ Done Memory Init @@ -424,7 +424,7 @@ mem_init: @ Set interrupt mask register @ - ldr r1, =CFG_ICMR_VAL + ldr r1, =CONFIG_SYS_ICMR_VAL ldr r2, =ICMR str r1, [r2] @@ -440,7 +440,7 @@ mem_init: @ set core clocks @ - ldr r2, =CFG_CCCR_VAL + ldr r2, =CONFIG_SYS_CCCR_VAL ldr r1, =CCCR str r2, [r1] @@ -463,7 +463,7 @@ mem_init: @ Turn on needed clocks @ ldr r1, =CKEN - ldr r2, =CFG_CKEN_VAL + ldr r2, =CONFIG_SYS_CKEN_VAL str r2, [r1] /*SET_LED 7 */ |