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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-12-10 15:02:20 +0530 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-12-18 21:14:01 -0500 |
| commit | cf04d0326bd1e24909cfe644c0c8676440a915b1 (patch) | |
| tree | b0363c4e98bc6eb2bfe4c5bf5c6ef76f40ccaf36 /board/phytec | |
| parent | 4892495e368da9462cd5c1c0d6498fe95b45192e (diff) | |
| download | u-boot-imx-cf04d0326bd1e24909cfe644c0c8676440a915b1.zip u-boot-imx-cf04d0326bd1e24909cfe644c0c8676440a915b1.tar.gz u-boot-imx-cf04d0326bd1e24909cfe644c0c8676440a915b1.tar.bz2 | |
ARM: AM43xx: clocks: Update DPLL details
Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is locked.
At different OPPs follwoing are the MPU locked frequencies.
OPP50 300MHz
OPP100 600MHz
OPP120 720MHz
OPPTB 800MHz
OPPNT 1000MHz
According to the latest DM following is the OPP table dependencies:
VDD_CORE VDD_MPU
OPP50 OPP50
OPP50 OPP100
OPP100 OPP50
OPP100 OPP100
OPP100 OPP120
So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
Following are the DPLL locking frequencies at OPP NOM:
Core locks at 1000MHz
Per locks at 960MHz
LPDDR2 locks at 266MHz
DDR3 locks at 400MHz
Touching AM33xx files also to get DPLL values specific to board but no
functionality difference.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'board/phytec')
0 files changed, 0 insertions, 0 deletions