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authorLars Poeschel <poeschel@lemonage.de>2013-04-03 04:37:52 +0000
committerTom Rini <trini@ti.com>2013-04-08 11:29:04 -0400
commitcecac32a06a71bc27fbcc8b5491400836952302d (patch)
treef66215f29fca1f8f69640942e7a6a0a1744ca2e5 /board/phytec
parent76b09b8561aa25d494aab31d94901fbda3526349 (diff)
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pcm051: Enable DDR PHY dynamic power down bit
This is done already for am335x in 59dcf970d11ebff5d9f4bbbde79fda584e9e7ad4 and also applies for pcm051. It powers down the IO receiver when not performing read which helps reducing the overall power consuption in low power states (suspend/standby). Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
Diffstat (limited to 'board/phytec')
-rw-r--r--board/phytec/pcm051/board.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 1708ac2..43d7b6e 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -104,7 +104,8 @@ static struct emif_regs ddr3_emif_reg_data = {
.sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
.sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
.zq_config = MT41J256M8HX15E_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY,
+ .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
+ PHY_EN_DYN_PWRDN,
};
#endif