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authorHeiko Schocher <hs@denx.de>2013-06-05 07:47:56 +0200
committerTom Rini <trini@ti.com>2013-06-18 09:12:38 -0400
commit49f783650020c62fdba4a78d4d272dca22d33662 (patch)
treea9b97016b29298b4b6becca98514f9b8e5462a72 /board/phytec
parent847e6693ccb529bf8346db62876f38f0c4e04ade (diff)
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arm, am33xx: move rtc32k_enable() to common place
move rtc32k_enable() to common place so all am33xx boards can use it. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Matt Porter <mporter@ti.com> Cc: Lars Poeschel <poeschel@lemonage.de> Cc: Tom Rini <trini@ti.com> Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Diffstat (limited to 'board/phytec')
-rw-r--r--board/phytec/pcm051/board.c16
1 files changed, 0 insertions, 16 deletions
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 93c611d..281f699 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -59,22 +59,6 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
/* DDR RAM defines */
#define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
-static void rtc32k_enable(void)
-{
- struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
- /*
- * Unlock the RTC's registers. For more details please see the
- * RTC_SS section of the TRM. In order to unlock we need to
- * write these specific values (keys) in this order.
- */
- writel(0x83e70b13, &rtc->kick0r);
- writel(0x95a4f1e0, &rtc->kick1r);
-
- /* Enable the RTC 32K OSC by setting bits 3 and 6. */
- writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41J256M8HX15E_RD_DQS,
.datawdsratio0 = MT41J256M8HX15E_WR_DQS,