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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-12-10 15:02:21 +0530 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-12-18 21:14:18 -0500 |
| commit | 965de8b91bddd1f5967240d1d44005719b09dd5e (patch) | |
| tree | dbcbdffdaaf14e8ace3eb1a911f27ace0352bbc6 /board/phytec | |
| parent | cf04d0326bd1e24909cfe644c0c8676440a915b1 (diff) | |
| download | u-boot-imx-965de8b91bddd1f5967240d1d44005719b09dd5e.zip u-boot-imx-965de8b91bddd1f5967240d1d44005719b09dd5e.tar.gz u-boot-imx-965de8b91bddd1f5967240d1d44005719b09dd5e.tar.bz2 | |
ARM: AM33xx+: Update ioregs to pass different values
Currently same value is programmed for all ioregs. This is not
the case for all SoC's like AM4372. So adding a structure for ioregs
and updating in all board files. And also return from config_cmd_ctrl()
and config_ddr_data() functions if data is not passed.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Fixup dxr2, cm_t335, adapt pcm051 rev3]
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'board/phytec')
| -rw-r--r-- | board/phytec/pcm051/board.c | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 68463e7..7e5e07f 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -50,6 +50,14 @@ const struct dpll_params *get_dpll_ddr_params(void) } #ifdef CONFIG_REV1 +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT41J256M8HX15E_IOCTRL_VALUE, + .cm1ioctl = MT41J256M8HX15E_IOCTRL_VALUE, + .cm2ioctl = MT41J256M8HX15E_IOCTRL_VALUE, + .dt0ioctl = MT41J256M8HX15E_IOCTRL_VALUE, + .dt1ioctl = MT41J256M8HX15E_IOCTRL_VALUE, +}; + static const struct ddr_data ddr3_data = { .datardsratio0 = MT41J256M8HX15E_RD_DQS, .datawdsratio0 = MT41J256M8HX15E_WR_DQS, @@ -81,10 +89,18 @@ static struct emif_regs ddr3_emif_reg_data = { void sdram_init(void) { - config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, + config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); } #else +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + static const struct ddr_data ddr3_data = { .datardsratio0 = MT41K256M16HA125E_RD_DQS, .datawdsratio0 = MT41K256M16HA125E_WR_DQS, @@ -116,7 +132,7 @@ static struct emif_regs ddr3_emif_reg_data = { void sdram_init(void) { - config_ddr(DDR_CLK_MHZ, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_data, + config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); } #endif |