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| author | Heiko Schocher <hs@denx.de> | 2013-07-30 10:48:54 +0530 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-08-15 08:51:10 -0400 |
| commit | 0660481a59cccd324fc2dfcad9734318a8c25a90 (patch) | |
| tree | ebebc64d145f50a26cf1cba98ba3e8ce4c3b9811 /board/phytec | |
| parent | 95cb69faeb45f6396a1336bff201a50ea1677d85 (diff) | |
| download | u-boot-imx-0660481a59cccd324fc2dfcad9734318a8c25a90.zip u-boot-imx-0660481a59cccd324fc2dfcad9734318a8c25a90.tar.gz u-boot-imx-0660481a59cccd324fc2dfcad9734318a8c25a90.tar.bz2 | |
ARM: AM33xx: Move s_init to a common place
s_init has the same outline for all the AM33xx based
board. So making it generic.
This also helps in addition of new Soc with minimal changes.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'board/phytec')
| -rw-r--r-- | board/phytec/pcm051/board.c | 48 |
1 files changed, 8 insertions, 40 deletions
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 17a98ff..f3bad76 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -30,8 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - /* MII mode defines */ #define MII_MODE_ENABLE 0x0 #define RGMII_MODE_ENABLE 0xA @@ -85,57 +83,27 @@ static struct emif_regs ddr3_emif_reg_data = { .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY | PHY_EN_DYN_PWRDN, }; -#endif -/* - * early system init of muxing and clocks. - */ -void s_init(void) +void set_uart_mux_conf(void) { - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ -#ifdef CONFIG_SPL_BUILD - save_omap_boot_params(); -#endif - - /* - * WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - -#ifdef CONFIG_SPL_BUILD - /* Setup the PLLs and the clocks for the peripherals */ - pll_init(); - - /* Enable RTC32K clock */ - rtc32k_enable(); - enable_uart0_pin_mux(); - uart_soft_reset(); - - gd = &gdata; - - preloader_console_init(); +} +void set_mux_conf_regs(void) +{ /* Initalize the board header */ enable_i2c0_pin_mux(); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); enable_board_pin_mux(); +} +void sdram_init(void) +{ config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -#endif } +#endif /* * Basic board specific setup. Pinmux has been handled already. |