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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-07-30 10:48:52 +0530 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-08-15 08:51:10 -0400 |
| commit | 94d77fb656d49f2b0efe2de5605a52c5145d2c3b (patch) | |
| tree | 0730083980308d786e0c44ceb61e4c156748b071 /board/phytec | |
| parent | fdce7b633a1de24456226b18527cc7900c34282a (diff) | |
| download | u-boot-imx-94d77fb656d49f2b0efe2de5605a52c5145d2c3b.zip u-boot-imx-94d77fb656d49f2b0efe2de5605a52c5145d2c3b.tar.gz u-boot-imx-94d77fb656d49f2b0efe2de5605a52c5145d2c3b.tar.bz2 | |
ARM: AM33xx: Cleanup dplls data
Locking sequence for all the dplls is same.
In the current code same sequence is done repeatedly
for each dpll. Instead have a generic function
for locking dplls and pass dpll data to that function.
This is derived from OMAP4 boards.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'board/phytec')
| -rw-r--r-- | board/phytec/pcm051/board.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 6291d03..17a98ff 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -44,6 +44,15 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; /* DDR RAM defines */ #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */ +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + static const struct ddr_data ddr3_data = { .datardsratio0 = MT41J256M8HX15E_RD_DQS, .datawdsratio0 = MT41J256M8HX15E_WR_DQS, |