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| author | Heiko Schocher <hs@denx.de> | 2013-06-04 11:00:57 +0200 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-06-18 10:40:06 -0400 |
| commit | 7ea7f689cab5bf715255e22c31aeefb23259afe5 (patch) | |
| tree | 89ddaebb7a3694b12ed2142ddcffca11277d2532 /board/phytec | |
| parent | 7b9c5d0bfd906a57a46336b5505550024a8a761f (diff) | |
| download | u-boot-imx-7ea7f689cab5bf715255e22c31aeefb23259afe5.zip u-boot-imx-7ea7f689cab5bf715255e22c31aeefb23259afe5.tar.gz u-boot-imx-7ea7f689cab5bf715255e22c31aeefb23259afe5.tar.bz2 | |
arm, am33xx: move uart soft reset code to common place
move uart soft reset code to common place and call
this function from board code, instead of copy and paste
this code for every board.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Matt Porter <mporter@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Tom Rini <trini@ti.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Tom Rini <trini@ti.com>
[trini: Fix igep0033 build, remove 'regval' on pcm051]
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'board/phytec')
| -rw-r--r-- | board/phytec/pcm051/board.c | 23 |
1 files changed, 1 insertions, 22 deletions
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 281f699..0cca8d7 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -39,9 +39,6 @@ DECLARE_GLOBAL_DATA_PTR; static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; -#ifdef CONFIG_SPL_BUILD -static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; -#endif /* MII mode defines */ #define MII_MODE_ENABLE 0x0 @@ -50,11 +47,7 @@ static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; -/* UART defines */ #ifdef CONFIG_SPL_BUILD -#define UART_RESET (0x1 << 1) -#define UART_CLK_RUNNING_MASK 0x1 -#define UART_SMART_IDLE_EN (0x1 << 0x3) /* DDR RAM defines */ #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */ @@ -125,22 +118,8 @@ void s_init(void) /* Enable RTC32K clock */ rtc32k_enable(); - /* UART softreset */ - u32 regval; - enable_uart0_pin_mux(); - - regval = readl(&uart_base->uartsyscfg); - regval |= UART_RESET; - writel(regval, &uart_base->uartsyscfg); - while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK) - != UART_CLK_RUNNING_MASK) - ; - - /* Disable smart idle */ - regval = readl(&uart_base->uartsyscfg); - regval |= UART_SMART_IDLE_EN; - writel(regval, &uart_base->uartsyscfg); + uart_soft_reset(); gd = &gdata; |