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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-03-24 17:52:22 +0100
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-03-24 17:52:22 +0100
commitb6379e15a70cc2e22486e5962927d9de374d877b (patch)
treece5c97f3754c29fa5d69a2da9b651ed59e876189 /board/phytec/pcm051/board.c
parent536121328eae940458f065608345b5fed8286859 (diff)
parent173ddc5b68fa41e55293d1095cafdc21fd11cf65 (diff)
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Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Diffstat (limited to 'board/phytec/pcm051/board.c')
-rw-r--r--board/phytec/pcm051/board.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 55bc018..1708ac2 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -61,7 +61,7 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
static void rtc32k_enable(void)
{
- struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
+ struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
/*
* Unlock the RTC's registers. For more details please see the
@@ -159,7 +159,7 @@ void s_init(void)
enable_board_pin_mux();
config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
- &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
#endif
}
@@ -199,8 +199,8 @@ static struct cpsw_slave_data cpsw_slaves[] = {
};
static struct cpsw_platform_data cpsw_data = {
- .mdio_base = AM335X_CPSW_MDIO_BASE,
- .cpsw_base = AM335X_CPSW_BASE,
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,