summaryrefslogtreecommitdiff
path: root/board/pcs440ep/init.S
diff options
context:
space:
mode:
authorHeiko Schocher <hs@pollux.denx.de>2007-06-22 19:11:54 +0200
committerHeiko Schocher <hs@pollux.denx.de>2007-06-22 19:11:54 +0200
commit566a494f592ae3b3c0785d90d4e1ba45574880c4 (patch)
tree933dceeaf04c7caa937774327f0b0ede81f9babc /board/pcs440ep/init.S
parent9912121f7ed804ea58fd62f3f230b5dcfc357d88 (diff)
downloadu-boot-imx-566a494f592ae3b3c0785d90d4e1ba45574880c4.zip
u-boot-imx-566a494f592ae3b3c0785d90d4e1ba45574880c4.tar.gz
u-boot-imx-566a494f592ae3b3c0785d90d4e1ba45574880c4.tar.bz2
[PCS440EP] upgrade the PCS440EP board:
- Show on the Status LEDs, some States of the board. - Get the MAC addresses from the EEProm - use PREBOOT - use the CF on the board. - check the U-Boot image in the Flash with a SHA1 checksum. - use dynamic TLB entries generation for the SDRAM Signed-off-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'board/pcs440ep/init.S')
-rw-r--r--board/pcs440ep/init.S41
1 files changed, 23 insertions, 18 deletions
diff --git a/board/pcs440ep/init.S b/board/pcs440ep/init.S
index 0eee4d8..36a40c9 100644
--- a/board/pcs440ep/init.S
+++ b/board/pcs440ep/init.S
@@ -87,27 +87,32 @@
.globl tlbtab
tlbtab:
- tlbtab_start
+ tlbtab_start
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
- tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR detection
+ * routine.
+ */
- /* PCI */
- tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
- /* USB 2.0 Device */
- tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
+ /* PCI */
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
- tlbtab_end
+ /* USB 2.0 Device */
+ tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
+
+ tlbtab_end