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authorwdenk <wdenk>2002-01-26 00:07:42 +0000
committerwdenk <wdenk>2002-01-26 00:07:42 +0000
commita1e329b41b473ab0b95ccad26147d404b1ac25b0 (patch)
treedd8da607d0b64deaa09b16d935be78ca7eee086b /board/pcippc2
parent2496efde2453c0fc51c962dfe60dd740ba4268bf (diff)
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Initial revision
Diffstat (limited to 'board/pcippc2')
-rw-r--r--board/pcippc2/pcippc2_fpga.h48
1 files changed, 48 insertions, 0 deletions
diff --git a/board/pcippc2/pcippc2_fpga.h b/board/pcippc2/pcippc2_fpga.h
new file mode 100644
index 0000000..b6206a4
--- /dev/null
+++ b/board/pcippc2/pcippc2_fpga.h
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PCIPPC2_FPGA_H_
+#define _PCIPPC2_FPGA_H_
+
+#define FPGA_VENDOR_ID 0x1310
+#define FPGA_DEVICE_ID 0x000d
+
+#define HW_FPGA0_INT 0x0000
+#define HW_FPGA0_UART1 0x0080
+#define HW_FPGA0_UART2 0x0100
+#define HW_FPGA0_RTC 0x2000
+#define HW_FPGA0_DOC 0x4000
+#define HW_FPGA1_RTC 0x0000
+#define HW_FPGA1_DOC 0x4000
+
+#define HW_FPGA0_INT_INTR_MASK 0x30
+#define HW_FPGA0_INT_INTR_STATUS 0x34
+#define HW_FPGA0_INT_INTR_EOI 0x40
+#define HW_FPGA0_INT_SERIAL_CONFIG 0x5c
+
+#define HW_FPGA0_WDT_CTRL 0x44
+#define HW_FPGA0_WDT_PROG 0x48
+#define HW_FPGA0_WDT_VAL 0x4c
+#define HW_FPGA0_WDT_REFRESH 0x50
+
+#endif